ADS1298读取数据时DRDY信号线空闲时为低电平

drdy  为输出脚，当drdy low, data ready, and drdy return to high on the first sclk falling edge. Din sould remain low for the entire read operation.

你好！
没碰到此类问题，可不可以抓个时序图给我们参考一下？ /DRDY,  DOUT, SCLK, Start 的波形。

看来还是要多看几遍手册啊，drdy low, data ready, and drdy return to high on the first sclk falling edge. Din sould remain low for the entire read operation这句我看第一遍都画出来了，但还是忘了

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