中途向ICAP中止写入部分比特流

嗨，
我正在尝试部分自我重新配置。
想法是通过介质将部分比特流发送到FPGA。
FPGA接收它（在多个块中）并将比特流写入ICAP。
当连接发生时，我的FPGA的行为会发生什么
发送部分比特流中途消失了？
我最终得到了半写的部分比特流。
那些在比特流部分重新配置的帧是否会被覆盖？
或者在推送数据之前是否需要DSYNC信号，该信号可能位于比特流的最后部分
到框架？
谢谢



以下为原文

Hi,

I'm experimenting with partial self-reconfiguration.
The idea is to send a partial bitstream over a medium to the FPGA.
The FPGA receives this (in multiple chunks) and writes the bitstream to the ICAP.

What happens with the behaviour of my FPGA when the connection would
disappear halfway the sending of the partial bitstream ? I'd end up with a half-written partial bitstream.
Will the frames, that are reconfigured in that part of the bitstream, be overwritten already ?
Or is there a need for a DSYNC signal, which p'bly is in the last part of the bitstream, before data is pushed
to the frames?

thx