测量组合电路面积的最佳方法是什么

你读过这个帖子吗？
你和rex_nyu有同样的学校作业吗？
测量组合电路面积的最佳方法....，该区域是否以LUT表示？
1.如果您正在讨论FPGA而不是ASIC，您可以测量和比较*资源使用情况*，表示为“LUT数量”。
在同一主题上有很多论坛主题。
随意查找和阅读它们。
2.请不要将'LUT'作为面积测量值。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
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以下为原文

Have you read this thread?
 
Do you have the same school assignment as rex_nyu?
 
best way to measure the area of a combinatorial circuit...., would that area be expressed in LUT's?
 
1.  If you are discussing FPGAs rather than ASICs, you can measure and compare *resource usage* expressed as 'number of LUTs'.  There are many forum threads on this same subject.  Feel free to find and read them.
 
2.  Please don't refer to '# of LUTs' as an area measurement.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

实际上，这不是一项学校作业。这是我的个人学习，更好地了解不同决策如何影响ISE工具的设计
因此，基于你的说法......比较不同设计方法对组合电路的资源利用率与LUT中表示的时序电路资源利用率的影响是否正确？
如果在Slice Registers中表达，或者是相同的事情？
问候，
亚历克斯



以下为原文

well actually is not a school assignment..It's for my personal study, to better understand how different decisions affect the design with the ISE tool
 
so therefore, based on your saying... It would be correct to compare the effects of different design methodologies on Resource utilization of a combinatorial circuit vs. Resource utilization of a sequential circuit expressed in LUTs?
 
or is the same thing if expressed in Slice Registers?
 
Regards,
Alex

为什么不根据寄存器和LUT进行比较？
不要忘记Block RAM和DSP48块。
一些设计和设计方法使用这些资源以及寄存器和LUT。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Why not compare based on both registers and LUTs?
 
And don't forget Block RAMs and DSP48 blocks.  Some designs and design approaches use these resources as well as registers and LUTs.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

因此......为了公平地表示一种方法或另一种方法对组合乘数面积的影响与对流水线乘法器面积的影响，需要将这种比较表示为LUTs与Slice寄存器？
或LUT与LUT？
简短的回答（至少对于FPGA来说 - 记住这是一个Xilinx论坛）是你的问题毫无意义。
FPGA通常具有逻辑元件，包括一个LUT加一个触发器以及一些额外的东西，如进位逻辑
可能有用也可能没用的多路复用器，具体取决于您使用的逻辑。
如果仅使用逻辑元件中的LUT，那么与使用相同的FPGA相比，您所占用的“区域”不会少
LUT及其相关寄存器。
因此，对于流水线与组合乘法器的情况，您应该这样做
发现每个最密集的版本将占用相同数量的逻辑元素，
除非您使用DSP48或MUL18x18等专用资源。
如果你想知道多少
每个设计区域都采用ASIC，然后找到适合所选择和测量的ASIC的综合工具
你的结果那样。
ASIC不会使用LUT作为门，也不会要求你浪费相邻的空间
在每个加法器阶段后不使用寄存器。
-  Gabor
-  Gabor



以下为原文

therefore....in order to make a fair representation of the effects of one methodology or another on the area of a combinatorial multiplier vs. effects on area of a pipelined multiplier would require to represent this comparison as LUTs vs Slice Registers? or LUTs vs LUTs?

The short answer (at least for FPGA's - remember that this is a Xilinx forum) is that your question makes no sense.
FPGA's typically have logic elements that consist of one LUT plus one flip-flop plus some extra stuff like carry logic
and multiplexers that may or may not be useful, depending on what you're using the logic for.
 
If you use just the LUT from a logic element, you take up no less "area" of the FPGA than using the same
LUT plus its associated register.  So for the case of pipelined vs. combinatorial multipliers, you should
find that the most densely packed versions of each will take up the same number of logic elements,
unless of course you use a dedicated resource like DSP48 or MUL18x18.  If you want to know how much
area each design takes in an ASIC, then find a synthesis tool which fits the ASIC of choice and measure
your results that way.  The ASIC won't use LUT's as gates nor will it require you to waste adjacent space when
not using a register after each adder stage.
 
-- Gabor
 
 
-- Gabor