请问C6455 Timer内部时钟源时钟频率是多少？

PLL1的Divder3是固定值1/6，不能修改的，所以没有Divider3寄存器。在数据手册第134页上有说明。
 
The divider ratio bits of dividers D2 and D3 are fixed at ÷3 and ÷6, respectively. The divider ratio bits of
dividers D4 and D5 are programmable through the PLL controller divider registers PLLDIV4 and PLLDIV5,
respectively.

Timer的internal clock是CPU clock/6，不是1/3 cpu clock。 

Timer的internal clock是CPU clock/6，不是1/3 cpu clock。 

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