断电后，当处于vBAT模式时RTCC时钟暂停

我有一个奇怪的问题与APIC24FJ128GA204配置，以保持RTCC关闭VBAT时，主电源断开，它的工作约70%，如果时间。当它工作正常的时候，我有一个DVM测量，刚刚从备份电池（大约2.6V）引出，当它不工作时，PIC绘制135NA或70NA和RTCC时钟暂停。我已经看了固件和硬件设置。我选择的晶体有一个80kHm的ESR，比我意识到的最大10K，这是问题吗？我还没有把一个范围放在水晶上看发生了什么。这里有一个配置比特的拷贝：//CONT4*PracMa配置文件DSWDTPS= DSWDTPS1F//深度睡眠看门狗定时器后标选择位（1:68 7194767 36（25.7天））。（DSWDT使用LPRC作为参考时钟）* PrimaMac配置，DSBRONE= OF//深度睡眠BOR允许位（DSBOR使能）α-PrAPMA配置DSWDTEN = OF//深度睡眠看门狗定时器启用（DSWDT启用）α-PracMA配置DSWEN＝ON//DSEN位使能（深睡眠由寄存器位DSEN控制）G PLLDIV＝禁用/ /USB 96兆赫PLL预分频器选择位（PLL禁用），γ-PracMA配置I2C1SEL =禁用/ /替代I2C1使能位（I2C1使用SCL1和SDA1管脚）IG WPFP＝WPFP127/ /写保护闪存页边界边界（第127页（0x1FC00））α-PracMA配置文件sOSSESE= ON//SOSC选择位（数字（SCLKI）模式）α-PrimaMac配置WSDBIN＝PS2500//窗口模式看门狗定时器窗口宽度选择（看门狗定时器窗口宽度为25%）PLLSS＝PLLYPRI/PLL二次选择配置位（PLL是由主振荡器馈送的）配置页选择（禁用），γ-PrAPMA配置，WpEnt= WPTMEM//段写保护结束页选择（写保护从WPFP到内存的最后一页）//CONT2×Prima配置文件POSCMD＝HS/主振荡器选择（HS振荡器启用）α-PrAPMA CONFIG WDTTCK＝LPRC/ / WDT Clock SouRCE选择位（WDT使用LPRC）{PrimaMaCorg OSCIOFCN= OF/OSCO PIN配置（OSCO／CKO/RA3函数作为CLKO（FoCC／2））γ-PracMA配置FCKSM＝CSDCMD/／时钟切换和故障安全时钟监视器配置位（时钟切换和故障安全时钟监视器被禁用）NOSCC＝PRI/ /初始振荡器选择（主振荡器（XT，HS，EC））α-PracMA配置，ALTCMPI＝CXCXYRB／/替代比较器输入位（C1CN在RB13上，C2Cin在RB9上，C3CN在RA0上）。DTCLK配置位）（S.Prack-ICOS= OF//内部外部切换（禁用）//OpFix1 Prima配置文件WDTPS＝PS327 68 / /看门狗定时器后定标器选择（1:327 68）×PrimaMac配置FFPSA＝PR128//WDT预分频比选择（1:128）标准看门狗定时器（μ-Pracm配置）FWDTEN＝OF//看门狗定时器使能（WDT硬件禁用；SWDTEN位禁用）μPrimaMac配置模块＝PGX1//仿真器引脚放置选择位（仿真器功能与PGEC1/PGED1共享）禁用-不包括ReT10）PrApRiga配置文件GWRP= OF//通用段写保护（允许写入程序存储器）



      以下为原文

    I have an odd problem with a PIC24FJ128GA204 configured to keep running the RTCC off vBAT when the main power is disconnected.

It works about 70% if the time. When it works correctly I have a DVM measuring just under 400nA being drawn from the backup battery (about 2.6V), when it doesn't work the PIC draws either 135nA or 70nA and the RTCC clock pauses.

I've looked at both the firmware and hardware setup. The crystal I selected has an ESR of 80kOhm, 10k more than the max I realised, could this be the issue?

I haven't got as far as putting a scope on the crystal to see what's happening.

Here is a copy of the Config Bits:

// CONFIG4
#pragma config DSWDTPS = DSWDTPS1F      // Deep Sleep Watchdog Timer Postscale Select bits (1:68719476736 (25.7 Days))
#pragma config DSWDTOSC = LPRC          // DSWDT Reference Clock Select (DSWDT uses LPRC as reference clock)
#pragma config DSBOREN = OFF             // Deep Sleep BOR Enable bit (DSBOR Enabled)
#pragma config DSWDTEN = OFF             // Deep Sleep Watchdog Timer Enable (DSWDT Enabled)
#pragma config DSSWEN = ON              // DSEN Bit Enable (Deep Sleep is controlled by the register bit DSEN)
#pragma config PLLDIV = DISABLED        // USB 96 MHz PLL Prescaler Select bits (PLL Disabled)
#pragma config I2C1SEL = DISABLE        // Alternate I2C1 enable bit (I2C1 uses SCL1 and SDA1 pins)
#pragma config IOL1WAY = ON             // PPS IOLOCK Set Only Once Enable bit (Once set, the IOLOCK bit cannot be cleared)
// CONFIG3
#pragma config WPFP = WPFP127           // Write Protection Flash Page Segment Boundary (Page 127 (0x1FC00))
#pragma config SOSCSEL = ON            // SOSC Selection bits (Digital (SCLKI) mode)
#pragma config WDTWIN = PS25_0          // Window Mode Watchdog Timer Window Width Select (Watch Dog Timer Window Width is 25 percent)
#pragma config PLLSS = PLL_PRI          // PLL Secondary Selection Configuration bit (PLL is fed by the Primary oscillator)
#pragma config BOREN = OFF               // Brown-out Reset Enable (Brown-out Reset Enable)
#pragma config WPDIS = WPDIS            // Segment Write Protection Disable (Disabled)
#pragma config WPCFG = WPCFGDIS         // Write Protect Configuration Page Select (Disabled)
#pragma config WPEND = WPENDMEM         // Segment Write Protection End Page Select (Write Protect from WPFP to the last page of memory)
// CONFIG2
#pragma config POSCMD = HS              // Primary Oscillator Select (HS Oscillator Enabled)
#pragma config WDTCLK = LPRC            // WDT Clock Source Select bits (WDT uses LPRC)
#pragma config OSCIOFCN = OFF           // OSCO Pin Configuration (OSCO/CLKO/RA3 functions as CLKO (FOSC/2))
#pragma config FCKSM = CSDCMD           // Clock Switching and Fail-Safe Clock Monitor Configuration bits (Clock switching and Fail-Safe Clock Monitor are disabled)
#pragma config FNOSC = PRI              // Initial Oscillator Select (Primary Oscillator (XT, HS, EC))
#pragma config ALTCMPI = CxINC_RB       // Alternate Comparator Input bit (C1INC is on RB13, C2INC is on RB9 and C3INC is on RA0)
#pragma config WDTCMX = WDTCLK          // WDT Clock Source Select bits (WDT clock source is determined by the WDTCLK Configuration bits)
#pragma config IESO = OFF               // Internal External Switchover (Disabled)
// CONFIG1
#pragma config WDTPS = PS32768          // Watchdog Timer Postscaler Select (1:32,768)
#pragma config FWPSA = PR128            // WDT Prescaler Ratio Select (1:128)
#pragma config WINDIS = OFF             // Windowed WDT Disable (Standard Watchdog Timer)
#pragma config FWDTEN = OFF             // Watchdog Timer Enable (WDT disabled in hardware; SWDTEN bit disabled)
#pragma config ICS = PGx1               // Emulator Pin Placement Select bits (Emulator functions are shared with PGEC1/PGED1)
#pragma config LPCFG = OFF//ON              // Low power regulator control (Disabled - regardless of RETEN)
#pragma config GWRP = OFF               // General Segment Write Protect (Write to program memory allowed)
#pragma config GCP = OFF                // General Segment Code Protect (Code protection is disabled)
#pragma config JTAGEN = OFF             // JTAG Port Enable (Disabled)