流模式下Virtex-5板上的示例程序AN65974不能正常工作

你好，
只有当没有完全填充任何DMA缓冲器时，才需要切换PKTAN信号。例如，假设你有6个大小为16K的DMA缓冲器。在前5个DMA缓冲器被填充后，它们将被包装（准备发送到USB），然后可以被提交（传输到USB外围设备）。假设第六DMA缓冲器部分被填充，并且FPGA没有更多的日期要发送。现在PKTACK信号被断言（拉低），因此缓冲区被包装。
你能让我们知道PC能接收多少数据、丢失多少数据以及FPGA实际上发送了多少数据、缓冲区计数和大小的详细信息、调试日志（如果有的话）？
当做，
- Madhu Sudhan



     以下为原文
  Hi,
 
The PKTEND signal needs to be toggled only when any DMA buffer is not completely filled. For example, assume that you have 6 DMA Buffers each of size 16K. After first 5 DMA Buffers are filled they will be wrapped (ready to be sent to the USB) and then can be committed (transferred to the USB Peripheral). Assume that the 6th DMA Buffer is partially filled and the FPGA has no more date to be sent. Now the PKTEND signal is asserted (pulled low), so the Buffer is wrapped.
 
Can you please let us know how much data is the PC able to receive, how much data is being lost and how much data is actually sent be the FPGA, details of your buffer count and size, Debug logs if any?
 
Regards,
- Madhu Sudhan

你好，
谢谢你的回复。实际上，我想理解为什么这个示例程序不起作用，因此我试着测试它的不同部分。事实上，当PKKAND被切换，而其余的程序保持不变，数据传输没有任何损失。
最后，上周我可以通过同一个平台（ViRTEX-5+EZ-USB FX3）通过另一个程序进行数据传输。就我个人而言，我认为AN6997程序可能在与FlagA／B有关的章节中有一些问题。
当做，
哈尼族



     以下为原文
  Hi,
 
Thank you for your reply. Actually, I wanted to understand why this sample program did not work, thereby I tried to test the different sections of it. As a matter of fact, When PKTEND was toggled, while the rest of the program remained unchanged, data was transferred without any lost.
 
Finally, last week I could have a data transferring via the same platform (Virtex-5 + EZ-USB FX3) by another program. Personally, I think AN65974 program may have some problems specially in the sections related to FlagA/B.
 
Regards,
Hani