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张海宝

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电源电压瞬态问题自动断电

大家好,我正在研究一个简单的电路与PIC12LF1501应该被激活的开关,保持自己的动力通过一个PMOS + NMOS对(PMOS器件绕过电源开关,NMOS驱动PMOS),并关闭自己关闭NIC晶体管通过PIC的RA5,这是主动驱动低。现在的问题是,当电源以这种方式关闭,端口RA5切换到H输出,一旦电源电压下降到约1伏-这就足以再次切换电源。这种情况总是发生,不管我如何配置RA5。我可能需要通过分频网络来驱动NMOS,将栅极电压降低到低于VTH @ 1伏特电源电压,但我想知道是否还有另一种解决方案(如果其他人遇到了同样的问题)。NMOS器件具有相当宽的VTH范围,在0.6到1.5伏特之间,这是复杂的,这只会带来3伏电源电压的问题。也许我最好在这里切换到一个NPN双极晶体管…谢谢你对这件事的任何想法!

以上来自于百度翻译


      以下为原文

    Hi all,
I'm working on a simple circuit with a PIC12LF1501 that is supposed to be activated with a switch, keeping itself powered up via a PMOS+NMOS pair (the PMOS device bypassing the supply switch, NMOS to drive the PMOS), and switch itself off by turning off the NMOS transistor through the PIC's RA5, which is actively driven low.

The problem now is that when the power is switched off in this manner, port RA5 switches to a H output as soon as the supply voltage drops to approximately 1 volt -- and this is enough to switch the power back on again. This always happens, regardless how I configure RA5.

I probably need to drive the NMOS via a divider network to lower the gate voltage to below Vth @ 1 volt supply voltage, but I wondered if there is another solution to this (and if other people experienced the same problem). It is also complicating that the NMOS device has a rather wide Vth range, between 0.6 and 1.5 volts -- which presents a bit of a problem with only 3 volts supply voltage. Perhaps I'd better switch to an NPN bipolar transistor here ...

Thanks in advance for any thoughts on this matter!

回帖(11)

李子跃

2018-11-16 15:08:55
在N-MOS门上有什么值下拉?对于类似的用途,我通常使用100-200 K.此外,I二极管或开关和PIC输出。

以上来自于百度翻译


      以下为原文

    What value pulldown do you have on the N-MOS gate? For similar uses I generally use 100-200k.
Also, I diode-or the switch and the PIC output.
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崔丹

2018-11-16 15:18:24
目前,没有下拉电阻,而是一个1UF的上限,有一个100K系列电阻从RA5,但这显然没有办法。我会用下拉电阻做一些测试,但是这当然有增加“ON”状态下的电源电流的缺点(我现在正处于一个桃色10UA,100K下拉这会增加四倍)。我也不能再增加NMOS门上的RC时间(现在0.1s),因为这样我就有一个问题,即开关必须持续一段时间,以确保它保持不变。但是谢谢你的快速回复!

以上来自于百度翻译


      以下为原文

    At the moment, there's no pull-down resistor but instead a 1uF cap, with a 100K series resistor from RA5, but that obviously doesn't do the trick. I'll do some testing with pull-down resistors, but that of course has the drawback of increasing the supply current drawn in the 'on' state (I'm at a peachy 10uA right now, and with 100K pull-down this would increase fourfold). I also can't increase the RC time (now 0.1s) on the NMOS gate any further, because then I'd have the problem that the switch must be pressed for that duration to make sure it stays on.
 
But thanks for the quick reply!
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张蕾

2018-11-16 15:28:35
HIE直接下拉是必须的,因为PIC引脚会在电源关闭时恢复到高阻抗(输入),留下NMOS门浮动。可能你所看到的是BOR的全部或部分的结果。

以上来自于百度翻译


      以下为原文

    Hi
 
The direct pull-down is a must because the PIC pins will revert to high impedance (inputs) when powering off, leaving the NMOS gate floating.
Probably what you are seeing is the result of a total or partial BOR.
 
 
Best regards
Jorge
 
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崔丹

2018-11-16 15:33:38
嗨,豪尔赫,这里的谜题是为什么NMOS栅极被拉高甚至电容器接地,它似乎是保护二极管的正电源电压:这是肖特基型,它具有不可忽略的漏电流。我把一个普通的硅二极管,加上一个1m的下拉电阻好的测量,现在一切都很好,只有一个小的增加on on the电流。嗯,快乐的微动力设计微笑:谢谢你的思考,最好的问候,

以上来自于百度翻译


      以下为原文

    Hi Jorge,
The puzzler here was why the NMOS gate was pulled high even with a capacitor to ground, and it appears that it was the protection diode to the positive supply voltage: that was a Schottky type, which has a non-negligible leakage current. I put in a normal silicon diode, plus a 1M pull-down resistor for good measure, and now things are fine, with only a small increase in on-state current.
 
Ah well, the joys of micropower design Smile:
 
Thanks for thinking along,
 
Best regards,
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