运行实施时序时波形错误

HI @ kogetsu
xdc文件中提到的时钟周期为3.7 ns，大约为270 Mhz。
但你说的是50 Mhz和66 Mhz的时钟频率。
你能澄清一下这个差异吗？
ThanksBharath -------------------------------------------------
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以下为原文

HI @kogetsu
 
The clock period mentioned in the xdc file is 3.7 ns which is around 270 Mhz.
but you are talking about 50 Mhz and 66 Mhz clock frequency. can you please clarify this discrepancy?
Thanks
Bharath
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你好@ nagabhar
当我第一次运行Implementation Timing Stimulation时，我将测试平台的时钟周期设置为4ns，如下所示：
总是开始 
＃2 clk = ~clk
结束
但是等待5-10分钟之后就没有波浪出现了。
然后我在测试平台中将时钟周期设置为20ns，如下所示：
总是开始 
＃10 clk = ~clk
结束
然后我看到了波浪，它是对的。
但是在我将时钟设置为16ns之后，波浪再次出现错误。（与第一个条件略有不同：当我将周期设置为4ns时，没有波，但是当我将周期设置为16ns时，有一个
错误的浪潮。）
这让我很困惑......我对实施时间刺激的步骤或设置有什么问题吗？
1.用testbench运行行为刺激
然后添加了XDC文件以获得时序分析（综合和实现全部通过）
3.根据时序分析的结果更改测试台的时钟周期
4.运行实施时间刺激
Thanls
kogetsu



以下为原文

Hi @nagabhar
 
When i firstly ran the Implementation Timing Stimulation, i set the clock period at 4ns in the testbench like this:
always begin
   #2 clk = ~clk
end
But just no wave came out after 5-10 minitues waiting.

 
 
 
Then i set the clock period at 20ns in the testbench like this:
always begin
   #10 clk = ~clk
end
Then i saw the wave and it was right.

 
 
 
But after i set the clock peiod at 16ns,the wave was wrong again.(A little different from the first condition:   when i set the period at 4ns,there was no wave,   but when i set the period at 16ns, there was a wrong wave.)

 
It really confused me...did i get something wrong with the steps or settings of Implementation Timing Stimulation?
1.Run the Behavioral Stimulation with testbench
2.Then added the XDC file to get the timing analysis(the synthesis and implementation are all passed)
3.Change the testbench's clock period based on the result of the timing analysis
4.Run the Implementation timing stimulation
 
Thanls
kogetsu 

你好@ nagabhar
哦，我在组合逻辑电路中找到了一个锁存器，我消除了它，然后关键路径变为13ns ......也许这就是问题所在？有没有什么方法可以最小化去除锁存器的频率成本？
谢谢
kogetsu



以下为原文

Hi @nagabhar
 
Oh,i found a latch in my combinatorial logic circuit and i eliminated it then the critical path become 13ns......maybe this is where the problem is?And Is there any method to minimize the frequency cost for removing the latch？
 
Thanks
kogetsu

HI @ kogetsu我不明白你的“关键路径”变成13 ns究竟是什么意思？
在进行后期实施之前，首先要检查设计的时序报告。您能否在时序报告中发送20 ns周期和16 ns周期值的设计？
您可以使用以下tcl命令生成报告文件（在打开实现的设计之后）
report_timing_summary -delay_type min_max -max_paths 10 -file timing_report.txt
ThanksBharath -------------------------------------------------
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如果提供的信息可以解决您的疑问/问题，请“接受为解决方案”。给予您认为有用的帖子。感谢.------------------------
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以下为原文

HI @kogetsu

I do not understand what exactly do you mean by "critical path" becoming  13 ns?


before doing a post implementation , first check the timing report of the design.
Can you please send in the timing reports with designs implemented  with 20 ns period  and 16 ns period value?
you can generate report files   with the following tcl command(after opening the implemented design)
report_timing_summary -delay_type min_max  -max_paths 10 -file timing_report.txt
Thanks
Bharath
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