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李刚

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[问答]

ST-Link/V2与HALT模式不兼容

大家好,
ST-Link / V2工具(所以SWIM接口)与HALT指令不兼容。

因此,为了调试和/或使用STMStudio,我不得不使用这种功能模式。
是否有任何解决方案可以优雅地解决问题?
#ST-LINK / V2

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Hi to all,
the ST-Link / V2 tool (so SWIM interface) is not compatible with the HALT instruction.

Therefore, for debugging and / or using STMStudio, I'm forced not to use this functional mode.
Is there any solution to elegantly circumvent the problem?
#st-link/v2

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李淳鑫

2018-10-30 18:17:10
根据文档,SWIM在停止期间仍然可以工作(但是,有效的SWIM连接将导致比其他情况下更高的功耗)。但调试模块没有。
在停止期间你想做什么,你不能做什么?设置或清除断点?
菲利普

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According to documentation, SWIM still works during halt (however, an active SWIM connection will result in higher power consumption than there would be otherwise). But the debug module doesn't.
What would you want to do during halt, that you can't? Set or clear a breakpoint?
Philipp
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杨阳

2018-10-30 18:25:38
正确的是,在WFI和WFE状态期间,调试器在低功耗状态下不能进入运行程序并读取内存。如果您需要此功能,则无法使用低功耗状态。
调试器唯一能做的就是重置芯片。这退出低功率状态。
- p

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Correct, the debugger cannot break into running program and read memory while it is in low power state - also during WFI and WFE states. If you want this ability, you cannot use low power states.
The only thing that the debugger can do is reset the chip. This exits the low power state.
-- p
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李刚

2018-10-30 18:31:24
嗨帕维尔,
感谢我确实遇到的问题,也就是说,在DEBUG期间的Active-HALT模式下,无法使用断点。
 
但是,这是一个不太重要的问题,因为在调试期间设备消耗的方式并不重要,因此我只是通过在最终编译或中间编译中启用它来禁用HALT功能,仅检查消耗。

以上来自于谷歌翻译


以下为原文




Hi Pavel,
Thanks for the confirm of the problem I actually encountered, that is, that in the Active-HALT mode during the DEBUG, can not possible to use the breakpoints.

However, it is a matter of little importance since during debug is not important how the device consumes and therefore simply I disable the HALT function by enabling it only in the final compilation or intermediate compilations, only to check the consumption.
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杨阳

2018-10-30 18:39:42
嗨Sisto,
如果可以从程序中检测调试器是否已连接,那么您不必编译两个变体。 RST_SR寄存器中的位3表示上次复位是由SWIM引起的。
- p

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以下为原文




Hi Sisto,
If it were possible to detect from the program whether debugger is connected, then you don't have to compile two variants. Bit 3 in RST_SR register indicates that last reset was caused by SWIM.
-- p
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