@ D2D,
您是否使用以下标准VHDL包启动VHDL代码:
库IEEE;使用IEEE.STD_LOGIC_1164.all;使用IEEE.STD_LOGIC_ARITH.all;使用IEEE.STD_LOGIC_SIGNED.all;
--Syed
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用,请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
--------------------------------------------------
-------------------
以上来自于谷歌翻译
以下为原文
@d2d,
Did you start your VHDL code with the following standard VHDL packages:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_SIGNED.all;
--Syed
---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
---------------------------------------------------------------------------------------------
@ D2D,
您是否使用以下标准VHDL包启动VHDL代码:
库IEEE;使用IEEE.STD_LOGIC_1164.all;使用IEEE.STD_LOGIC_ARITH.all;使用IEEE.STD_LOGIC_SIGNED.all;
--Syed
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用,请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
--------------------------------------------------
-------------------
以上来自于谷歌翻译
以下为原文
@d2d,
Did you start your VHDL code with the following standard VHDL packages:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_SIGNED.all;
--Syed
---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
---------------------------------------------------------------------------------------------
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