在DIVW和DIV中断会发生什么

你好WoRo！
 
 我不知道STM8核如何实现DIV / DIVW指令。
 STM8勘误表文档提供了一些见解，因为在ISR中始终存在“意外的DIV / DIVW指令”子部分。
 当中断执行DIV / DIVW指令而另一个事件中断IRET指令时，会发生此错误。
 似乎未使用的CC位在DIV / DIVW执行中起一定作用。
 在我看来，专用硬件单元处理DIV / DIVW指令，当其结果准备好时，所涉及的寄存器被更新。这些更新可能由这些未使用的位之一（通常为空）强制执行，但只有STM8核心设计人员才知道会发生什么。
 
 我认为ISR应该避免这些指令，但它可能过于保守......
 
 EtaPhi



以下为原文





Hello WoRo!

I don't know how STM8 core implements DIV/DIVW instructions.
STM8 errata documents provide some insight, as there is always an ''Unexpected DIV/DIVW instruction in ISR'' sub-section.
This error happens when an interrupt executes a DIV/DIVW instruction and another event interrupts the IRET instruction.
It seems that unused CC bits play some role in DIV/DIVW execution.
In my opinion, a dedicated hardware unit processes DIV/DIVW instructions and when its result is ready, the involved registers are updated. This update may be forced by one of these unused bits (which are usually null), but only the STM8 core designers know what happens.

I think that ISRs should avoid these instructions, but it may be too much conservative...

EtaPhi

我通过模拟中断堆栈帧尝试运行IRET指令失败了。
 
 无论要恢复的CC值是什么，输出都是相同的：没有意外的X或Y寄存器值。
 CC的第6位（未定义）似乎对IRET执行没有影响。
 出于这个原因，我认为DIV / DIVW指令使用影子寄存器，用户代码无法访问，以及对用户也隐藏的触发器。
 
 对不起，您的问题似乎没有答案。
 
 问候，
 
 EtaPhi



以下为原文





I unsuccessfully tried to exercise IRET instruction by simulating an interrupt stack frame.

Whatever the CC value to restore is, the output is the same: no unexpected X or Y register value.
It seems that bit 6 of CC, which is undefined, has no effect on IRET execution.
For this reason, I suppose that DIV/DIVW instructions use shadow registers, which user code can't access, and a flip/flop which is hidden to the user too.

Sorry, it seems that there is no answer to your question.

Regards,

EtaPhi