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[问答]

PlanAhead实施出错

大家好,我在zedboard中使用XPS创建了一个IP核。
我在PA中运行实现,有两个错误。
一个是“[Pack 2309]太多的”IOB“类型的粘合复合物被发现适合这种设备。”
另一个是“[Map 237]设计太大而无法适应设备。请查看”设计摘要“部分,了解设计的资源需求超出了设备中的可用资源。请注意报告的切片数量
可能无法准确反映,因为他们的包装可能尚未完成。“
然而,该设计并不复杂,并且不像所描述的尖端那么大。
我在ISE中模拟了逻辑组件。
这是PA中的资源表。
我怎么能解决这个问题?
谢谢。

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以下为原文

hi,everyone,I created a IP core using XPS in zedboard.
   I run the implementation in PA,and  there are two errors.
One is that " [Pack 2309] Too many bonded comps of type "IOB" found to fit this device." ,and the other is that "[Map 237] The design is too large to fit the device. Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as their packing might not have been completed."

However, the design is not complicated and is not too large as the tips described.
I have simulated  the logic component in ISE.
And this is the resource table in PA.


How could I do with this problem?
Thank you.

回帖(6)

李裕伦

2018-10-25 15:23:48
你想用哪种IP?
如果它与设备无关,我建议尝试使用其他设备。
这将确认问题是否与IP或设备部件有关。
问候
Sikta

以上来自于谷歌翻译


以下为原文

Which IP are you trying to use? If it has nothing to do with a device, I would suggest trying with a different device.
 
This will confirm if the problem has to do with IP or the device part.
 
Regards
Sikta
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石俊梅

2018-10-25 15:40:27
嗨,
错误表示设计中的IO端口数超过了设备中的IOB数。
检查设计中的顶级端口,看看是否可以减少它们。
否则瞄准更大的设备。
谢谢,
迪皮卡。
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以上来自于谷歌翻译


以下为原文

Hi,
 
The error says that the number of IO ports in the design exceeds the number of IOB's in the device.
 
Check the top level ports in the design and see if you can reduce them. Else target a bigger device.
 
Thanks,
Deepika.
Thanks,
Deepika.
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刘溪

2018-10-25 15:45:38
你好
资源表清楚地表明您的设备使用了136%的IO(过度使用)设备中存在的IO数量。
你必须要处理这个问题,看起来你正在将逻辑端口作为顶级引脚。
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以上来自于谷歌翻译


以下为原文

Hi
 
The resource table clearly indicates that your desing is using 136% of IO's(overutilizing) the number of IO's present in the device.
 
You have to take care of this,looks like you are making logical ports also as top level pins.
Regards,

Satish

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毕建录

2018-10-25 15:51:39
我只是写了一个非常简单的ip核心,它只显示一个充满红色像素的静态图片。
主要问题是,任何选项是否可以优化合成和实现,绝对不是缺乏芯片资源。
我重写了逻辑电路,问题就没了。

以上来自于谷歌翻译


以下为原文

I just write a very easy ip core , it just displays a static picture ,full of red pixels. the main problem is that whether  any  option can optimize the sythesis  and implementation, it is absolutely not  the lack of the chip resource.
 
I rewrite the logic circuit, and the problem gone.
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