Virtex-6 FPGA上的可重配置LUT无法打包

用于Virtex 6设计的可重配置LUT（CFGLUT）可能被封装到FPGA的输出逻辑OLOGICE1而不是SLICEM上的LUT。
我的设计涉及使用存在于与CFGLUT相同的片中的FF（用于流水线操作）来注册CFGLUT的双输出，并将其作为其他模块的输入。
但是，当我给出物理约束来在ucf文件中的CLB的同一片（SLICEM）上打包CFGLUT和FF时，我得到一个“Map Error”报告它无法打包。
请帮助



以下为原文

The reconfigurable LUTs  (CFGLUT) for a Virtex 6 design is possibly getting packed to the Output Logic OLOGICE1s of the FPGA instead of the LUTs on the SLICEM. My design involves registering the dual outputs of the CFGLUTs using FFs present in the same slice as that of the CFGLUTs (for pipelining) and giving it as input to other modules. However, when I am giving physical constraints to pack the CFGLUTs and FFs on the same slice (SLICEM) of a CLB in the ucf file, I am obtaining a "Map Error" reporting its inability to pack. Kindly help