带过滤器的XDC约束无法正常工作

了解层次结构在Vivado中的工作原理非常重要 - 如果不正确理解它，很难完成任何工作。
您正在使用的示例也是可怕的示例 - 它们是来自UCF的相当直接的翻译，并且不是在XDC中获取对象的推荐方式（并且，是的，我知道它们来自Xilinx IP ......）。
在XDC中，分层名称不仅仅是具有层次结构分隔字符的名称，而实际上是其他元素中其他元素中的元素......
因此，获取实例化b_inst内部的单元c_inst的正确方法是实例化a_inst，该实例化是在设计的顶层实例化的。
get_cells a_inst / b_inst / c_inst
-hier选项可以在任何地方查找单元格
get_cells -hier c_inst
还会找到c_inst
你做不到
get_cells * c_inst
get_cells * / c_inst
这些通配符都不会与这种通配符相符
get_cells * / * / c_inst
会找到c_inst
“。”
仅仅是一个角色。
确实，我们找到包含“。”的名称。
- 通常作为生成语句的结果，但是单元格
d_inst / e_inst / f_inst.g_inst
是实例化e_inst中的单元格“f_inst.g_inst”，它位于d_inst内
这只是冰山一角。
您还可以执行许多其他操作 - 例如使用filter命令。
但最好了解filter命令的作用;
根据其属性过滤对象。
当然，这导致了“什么是属性”和“存在什么样的属性”这个问题，以及“什么是'NAME'属性，以及你可以用它做什么......”
然后你会进入类似“范围”约束文件（MIG xdc文件所在的文件，这就是为什么你在顶层使用它们时遇到麻烦）......
Xilinx提供涵盖这些主题的课程 - 特别是本课程和本课程
除此之外，我确信（某处）所有这些都在手册中，但不是在一个地方......
Avrum
在原帖中查看解决方案



以下为原文

It is pretty important to understand how hierarchy works in Vivado - its pretty hard to get anything done without properly understanding it.
 
The examples you are using are also terrible examples - they are fairly literal translations from UCF, and are not the recommended way of getting objects in XDC (and, yes, I know they come from Xilinx IP...).
 
In XDC, hierarchical names are not simply names that have hierarchy separation characters in them, but actually elements within other elements within other elements...
 
So, the correct way to get a cell c_inst which is inside the instantiation b_inst, which is inside the instantiation a_inst which is instantiated at the top level of the design is
 
get_cells a_inst/b_inst/c_inst
 
The -hier option finds cells anywhere, so
 
get_cells -hier c_inst
 
will also find c_inst
 
You cannot do
 
get_cells *c_inst
get_cells */c_inst
 
neither of these wildcards will match the hierarhcy, althoug
 
get_cells */*/c_inst
 
will find c_inst
 
The "." is merely a character. It is true that we find names that contain "." - often as the result of a generate statement, but the cell
 
d_inst/e_inst/f_inst.g_inst
 
is the cell "f_inst.g_inst" inside the instantiation e_inst, which is inside d_inst
 
This is just the tip of the iceberg. There are many other things you can do - like using the filter command. But its best to understand what the filter command does; filter objects based on thier properties. This, of course, leads to the question "what are properties" and "what kind of properties exists", and "what is the 'NAME' property, and what can you do with it..."
 
Then you get in to things like "scoped" constraint files (which the MIG xdc files are, which is why you are having trouble with them when using them at the top level)...
 
Xilinx offers classes that cover these topics - particularly this one and this one
 
Other than that, I am sure that (somewhere) all of this is in the manuals, but not in one single spot...
 
Avrum
 
 
View solution in original post

了解层次结构在Vivado中的工作原理非常重要 - 如果不正确理解它，很难完成任何工作。
您正在使用的示例也是可怕的示例 - 它们是来自UCF的相当直接的翻译，并且不是在XDC中获取对象的推荐方式（并且，是的，我知道它们来自Xilinx IP ......）。
在XDC中，分层名称不仅仅是具有层次结构分隔字符的名称，而实际上是其他元素中其他元素中的元素......
因此，获取实例化b_inst内部的单元c_inst的正确方法是实例化a_inst，该实例化是在设计的顶层实例化的。
get_cells a_inst / b_inst / c_inst
-hier选项可以在任何地方查找单元格
get_cells -hier c_inst
还会找到c_inst
你做不到
get_cells * c_inst
get_cells * / c_inst
这些通配符都不会与这种通配符相符
get_cells * / * / c_inst
会找到c_inst
“。”
仅仅是一个角色。
确实，我们找到包含“。”的名称。
- 通常作为生成语句的结果，但是单元格
d_inst / e_inst / f_inst.g_inst
是实例化e_inst中的单元格“f_inst.g_inst”，它位于d_inst内
这只是冰山一角。
您还可以执行许多其他操作 - 例如使用filter命令。
但最好了解filter命令的作用;
根据其属性过滤对象。
当然，这导致了“什么是属性”和“存在什么样的属性”这个问题，以及“什么是'NAME'属性，以及你可以用它做什么......”
然后你会进入类似“范围”约束文件（MIG xdc文件所在的文件，这就是为什么你在顶层使用它们时遇到麻烦）......
Xilinx提供涵盖这些主题的课程 - 特别是本课程和本课程
除此之外，我确信（某处）所有这些都在手册中，但不是在一个地方......
Avrum



以下为原文

It is pretty important to understand how hierarchy works in Vivado - its pretty hard to get anything done without properly understanding it.
 
The examples you are using are also terrible examples - they are fairly literal translations from UCF, and are not the recommended way of getting objects in XDC (and, yes, I know they come from Xilinx IP...).
 
In XDC, hierarchical names are not simply names that have hierarchy separation characters in them, but actually elements within other elements within other elements...
 
So, the correct way to get a cell c_inst which is inside the instantiation b_inst, which is inside the instantiation a_inst which is instantiated at the top level of the design is
 
get_cells a_inst/b_inst/c_inst
 
The -hier option finds cells anywhere, so
 
get_cells -hier c_inst
 
will also find c_inst
 
You cannot do
 
get_cells *c_inst
get_cells */c_inst
 
neither of these wildcards will match the hierarhcy, althoug
 
get_cells */*/c_inst
 
will find c_inst
 
The "." is merely a character. It is true that we find names that contain "." - often as the result of a generate statement, but the cell
 
d_inst/e_inst/f_inst.g_inst
 
is the cell "f_inst.g_inst" inside the instantiation e_inst, which is inside d_inst
 
This is just the tip of the iceberg. There are many other things you can do - like using the filter command. But its best to understand what the filter command does; filter objects based on thier properties. This, of course, leads to the question "what are properties" and "what kind of properties exists", and "what is the 'NAME' property, and what can you do with it..."
 
Then you get in to things like "scoped" constraint files (which the MIG xdc files are, which is why you are having trouble with them when using them at the top level)...
 
Xilinx offers classes that cover these topics - particularly this one and this one
 
Other than that, I am sure that (somewhere) all of this is in the manuals, but not in one single spot...
 
Avrum
 
 

嗨，
我试图通过修改自动生成的MIG XDC来制作XDC。
>>我可以问你为什么要修改MIG生成的XDC？
据我所知，当MIGis生成并添加到您的自定义设计中时，Vivado将在综合/实现期间检测并读取IPgenerated XDC，您可以在编译顺序报告中找到它。
您可以在example_top.xdc或您自己的xdc中添加其他constarints
如果XDC保持不变，您是否看到任何错误，您能分享我们的流量和错误日志/快照吗？
你使用哪个Vivado verison？
问候，
Vanitha
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以下为原文

Hi,
 
I am trying to make XDC by modifying automatically generated XDC of MIG.
>> Can I ask why do you want to modify MIG generated XDC?
To my knowledge when MIG is generated and added to your custom design, Vivado will detect and read IP generated XDC during Synthesis/implementation, you can find it in compile order report.
You can add your other constarints in example_top.xdc or your own xdc
Did you see any error if the XDC is left as is, can you share us your flow and error log /snapshot?
Which Vivado verison are you using?
 
 
Regards,
Vanitha
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你好，
我评论了你的问题。
我试图通过修改自动生成的MIG XDC来制作XDC。
>>我可以问你为什么要修改MIG生成的XDC？
因为我使用MIG7 PHY定制控制器（非MIG控制器）。
层次结构与MIG生成的XDC的原始层次结构不同。
据我所知，当MIGis生成并添加到您的自定义设计中时，Vivado将在综合/实现期间检测并读取IPgenerated XDC，您可以在编译顺序报告中找到它。
您可以在example_top.xdc或您自己的xdc中添加其他constarints
如果XDC保持不变，您是否看到任何错误，您能分享我们的流量和错误日志/快照吗？
我想我解决了这个问题。
但我遇到了另外的错误消息，如下所示。
http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/MIG-PHY-P-amp-R-issue-Place-30-370-An-unconstrained-Phaser/td-p/484402
不知何故，vivado可能仍然没有找到分层细胞......
你使用哪个Vivado verison？
2014.1
谢谢。



以下为原文

Hello, 
 
I commented on your questions.
 
I am trying to make XDC by modifying automatically generated XDC of MIG.
>> Can I ask why do you want to modify MIG generated XDC?
Because I am using customized controller(Not MIG controller) with MIG7 PHY.
Hierarchy is different from original one of MIG generated XDC.
 
To my knowledge when MIG is generated and added to your custom design, Vivado will detect and read IP generated XDC during Synthesis/implementation, you can find it in compile order report.
You can add your other constarints in example_top.xdc or your own xdc
Did you see any error if the XDC is left as is, can you share us your flow and error log /snapshot?
I suppose I resolved this problem. but I met another error messages like below.
http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/MIG-PHY-P-amp-R-issue-Place-30-370-An-unconstrained-Phaser/td-p/484402
somehow vivado might still not find hierachical cells...
 
Which Vivado verison are you using?
2014.1
 
 
Thanks.