删除单元格后放置错误

嗨，
为了适应ILA探测信号，我必须减少一些逻辑，因为FPGA已经过度使用。
对remove_cell执行某些冗余逻辑后，放置失败，并显示以下消息：
[地点30-53] IDELAYCTRL实例 'axi_top_0 / axi_m2m_m0 /安装/ slave_fpga_gen.axi_chip2chip_slave_phy_inst / slave_sio_phy.axi_chip2chip_sio_input_inst / idelayctrl_gen.IDELAYCTRL_inst' 和 'i_fpga_a_bvci_c2c_top / axi_sysreg_s0 /安装/ master_fpga_gen.axi_chip2chip_master_phy_inst / master_sio_phy.axi_chip2chip_sio_input_inst / idelayctrl_gen.IDELAYCTRL_inst' 具有相同IODELAY_GROUP
'C2C_PHY_group'但它们的RST信号不同。
在运行实现之前，都删除了axi_top_0和i_fpga_a_bvci_c2c_top。
但是这个地方错误来自这两个单元格的IDELAYCTRL实例。
除了重置之外，REFCLK也会出现错误。
请帮忙。
感谢致敬，
Amitra



以下为原文

Hi,

To accomodate ILA probe signals, I have to reduce some logic since FPGA is already over utilized. After doing remove_cell for some redundant logic the placement failed with the following message:

[Place 30-53] IDELAYCTRL instances 'axi_top_0/axi_m2m_m0/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/slave_sio_phy.axi_chip2chip_sio_input_inst/idelayctrl_gen.IDELAYCTRL_inst' and 'i_fpga_a_bvci_c2c_top/axi_sysreg_s0/inst/master_fpga_gen.axi_chip2chip_master_phy_inst/master_sio_phy.axi_chip2chip_sio_input_inst/idelayctrl_gen.IDELAYCTRL_inst' have same IODELAY_GROUP 'C2C_PHY_group' but their RST signals are different.


Both axi_top_0 and i_fpga_a_bvci_c2c_top were removed before running implementation. But the place error is coming from the IDELAYCTRL instances of these two cells. Apart from reset, the error is also coming for REFCLK.

Please help.

Thanks and regards,
Amitra