嗨,
我正在使用的设计不会通过MAP。
我正在运行ISE 13.1。
我收到以下错误:
将设计映射到LUT ......
错误:TSDatabase:19 - 处理
tiMESPEC定义
TS_D2_TO_T2 = FROM:D2_CLK:TO:FFS:TIG:
没有定义名为“D2_CLK”的TNM,TPSYNC或用户组。
错误:TSDatabase:19 - 处理TIMESPEC定义
TS_J2_TO_D2 = FROM:FFS:TO:D2_CLK:TIG:
没有定义名为“D2_CLK”的TNM,TPSYNC或用户组。
错误:TSDatabase:19 - 处理TIMESPEC定义
TS_J3_TO_D2 = FROM:FFS:TO:D2_CLK:TIG:
没有定义名为“D2_CLK”的TNM,TPSYNC或用户组。
错误:TSDatabase:19 - 处理TIMESPEC定义
TS_J4_TO_D2 = FROM:FFS:TO:D2_CLK:TIG:
没有定义名为“D2_CLK”的TNM,TPSYNC或用户组。
INTERNAL_ERROR:Pack:pkibangm.c:2584:1.87 - 发现4次timespec错误
它是Virtex 6上的一个大型设计。有一个PCIe端点(大部分代码直接来自Xilinx)和许多Coregen单元。
现在,我不知道如何处理这些错误。
在ucf文件中,没有像抱怨的TIMESPEC定义(“TS_D2_TO_T2”等)或任何类似的定义。
项目中只有一个ucf文件。
还没有名称为“D2_CLK”的TNM或类似名称。
所以我只是不明白TIMESPEC的起源是什么?
我在项目的所有文件中搜索了“* TS_J2 *”模式。
我在此消息下面列出了输出。
它有四个文件:三个报告错误(xmsg,.map和.mpr文件),*和*一次在综合报告中。
后者列出了一个时序约束,“TS_J2_TO_D2 = FROM TIMEGRP”FFS“TO TIMEGRP”D2_CLK“TIG;”,但是综合工具从哪里得到这个,因为我找不到将这个定义输入到工具的任何地方?
此外,合成不抱怨错过“D2_CLK”所以我猜它是在某处发现的。
但我也无法理解,因为如果我搜索模式“D2_CLK”(命令“grep -i -r -C 3 D2_CLK。”),它会找到与搜索TS_J2完全相同的条目 - 所以我不能
了解D2_CLK是什么或来自哪里。
任何帮助表示赞赏!
卡尔
$ grep -i -r -C 3 TS_J2。
./_xmsgs/map.xmsgs-No TNM,TPSYNC或名为& quot; D2_CLK& quot;的用户组。
被定义为。
./_xmsgs/map.xmsgs-
./_xmsgs/map.xmsgs-
./_xmsgs/map.xmsgs:Processing TIMESPEC定义TS_J2_TO_D2 = FROM:FFS:TO:D2_CLK:TIG:
./_xmsgs/map.xmsgs-No TNM,TPSYNC或名为& quot; D2_CLK& quot;的用户组。
被定义为。
./_xmsgs/map.xmsgs-
./_xmsgs/map.xmsgs-
-
./xilinx_pcie_2_0_ep_v6.syr-(51.1%逻辑,48.9%路线)
./xilinx_pcie_2_0_ep_v6.syr-
./xilinx_pcie_2_0_ep_v6.syr-============================================
=============================
./xilinx_pcie_2_0_ep_v6.syr:Timing constraint:TS_J2_TO_D2 = FROM TIMEGRP“FFS”TO TIMEGRP“D2_CLK”TIG;
./xilinx_pcie_2_0_ep_v6.syr-时钟周期:1.086ns(频率:920.641MHz)
./xilinx_pcie_2_0_ep_v6.syr-路径/目标端口总数:15/15
./xilinx_pcie_2_0_ep_v6.syr-失败的路径/端口数:0(0.00%)/ 0(0.00%)
-
./xilinx_pcie_2_0_ep_v6_map.map-TS_D2_TO_T2 = FROM:D2_CLK:TO:FFS:TIG:
./xilinx_pcie_2_0_ep_v6_map.map-未定义TNM,TPSYNC或名为“D2_CLK”的用户组。
./xilinx_pcie_2_0_ep_v6_map.map-ERROR:TSDatabase:19 - 处理TIMESPEC定义
./xilinx_pcie_2_0_ep_v6_map.map:TS_J2_TO_D2 = FROM:FFS:TO:D2_CLK:TIG:
./xilinx_pcie_2_0_ep_v6_map.map-未定义TNM,TPSYNC或名为“D2_CLK”的用户组。
./xilinx_pcie_2_0_ep_v6_map.map-ERROR:TSDatabase:19 - 处理TIMESPEC定义
./xilinx_pcie_2_0_ep_v6_map.map-TS_J3_TO_D2 = FROM:FFS:TO:D2_CLK:TIG:
-
./xilinx_pcie_2_0_ep_v6_map.mrp-TS_D2_TO_T2 = FROM:D2_CLK:TO:FFS:TIG:
./xilinx_pcie_2_0_ep_v6_map.mrp-未定义TNM,TPSYNC或名为“D2_CLK”的用户组。
./xilinx_pcie_2_0_ep_v6_map.mrp-ERROR:TSDatabase:19 - 处理TIMESPEC定义
./xilinx_pcie_2_0_ep_v6_map.mrp:TS_J2_TO_D2 = FROM:FFS:TO:D2_CLK:TIG:
./xilinx_pcie_2_0_ep_v6_map.mrp-未定义TNM,TPSYNC或名为“D2_CLK”的用户组。
./xilinx_pcie_2_0_ep_v6_map.mrp-ERROR:TSDatabase:19 - 处理TIMESPEC定义
./xilinx_pcie_2_0_ep_v6_map.mrp-TS_J3_TO_D2 = FROM:FFS:TO:D2_CLK:TIG:
$
以上来自于谷歌翻译
以下为原文
Hi,
A design I'm working with won't go through MAP. I'm running ISE 13.1. I get the following errors:
Mapping design into LUTs...ERROR:TSDatabase:19 - Processing TIMESPEC definition TS_D2_TO_T2=FROM:D2_CLK:TO:FFS:TIG: No TNM, TPSYNC or user group named "D2_CLK" is defined.ERROR:TSDatabase:19 - Processing TIMESPEC definition TS_J2_TO_D2=FROM:FFS:TO:D2_CLK:TIG: No TNM, TPSYNC or user group named "D2_CLK" is defined.ERROR:TSDatabase:19 - Processing TIMESPEC definition TS_J3_TO_D2=FROM:FFS:TO:D2_CLK:TIG: No TNM, TPSYNC or user group named "D2_CLK" is defined.ERROR:TSDatabase:19 - Processing TIMESPEC definition TS_J4_TO_D2=FROM:FFS:TO:D2_CLK:TIG: No TNM, TPSYNC or user group named "D2_CLK" is defined.INTERNAL_ERROR:Pack:pkibangm.c:2584:1.87 - 4 timespec errors found It's a large design on a Virtex 6. There's a PCIe endpoint (with large portions of code directly from Xilinx) and a number of Coregen units.
Now, I don't know what to do with these errors. In the ucf file, there are no TIMESPEC definitions like the ones complained about ("TS_D2_TO_T2" and so on) or anything similar. There's just one ucf file in the project. There's also no TNM or similar named to "D2_CLK". So I just don't understand what the TIMESPEC comes from in the first place?
I searched for the pattern "*TS_J2*" in all files of the project. I listed the output below this message. It's found in four files: Three reporting the error (xmsg, the .map and .mpr files), *and* once in the Synthesis Report. The latter lists a timing constraint, "TS_J2_TO_D2 = FROM TIMEGRP "FFS" TO TIMEGRP "D2_CLK" TIG;", but where does the synthesis tool get this from since I can't find anywhere where this definition is inputted to the tools? Also, synthesis don't complain about missing "D2_CLK" so I guesse it is found somewhere. But I can't understand that either, since if I search for the pattern "D2_CLK" (command "grep -i -r -C 3 D2_CLK .") it finds exactly the same entries as searching for TS_J2 - so I can't understand what D2_CLK is or where it comes from either.
Any help is appreciated!
Carl
$ grep -i -r -C 3 TS_J2 ../_xmsgs/map.xmsgs-No TNM, TPSYNC or user group named "D2_CLK" is defined../_xmsgs/map.xmsgs-./_xmsgs/map.xmsgs-./_xmsgs/map.xmsgs:Processing TIMESPEC definition TS_J2_TO_D2=FROM:FFS:TO:D2_CLK:TIG:./_xmsgs/map.xmsgs-No TNM, TPSYNC or user group named "D2_CLK" is defined../_xmsgs/map.xmsgs-./_xmsgs/map.xmsgs---./xilinx_pcie_2_0_ep_v6.syr- (51.1% logic, 48.9% route)./xilinx_pcie_2_0_ep_v6.syr-./xilinx_pcie_2_0_ep_v6.syr-=========================================================================./xilinx_pcie_2_0_ep_v6.syr:Timing constraint: TS_J2_TO_D2 = FROM TIMEGRP "FFS" TO TIMEGRP "D2_CLK" TIG;./xilinx_pcie_2_0_ep_v6.syr- Clock period: 1.086ns (frequency: 920.641MHz)./xilinx_pcie_2_0_ep_v6.syr- Total number of paths / destination ports: 15 / 15./xilinx_pcie_2_0_ep_v6.syr- Number of failed paths / ports: 0 (0.00%) / 0 (0.00%)--./xilinx_pcie_2_0_ep_v6_map.map- TS_D2_TO_T2=FROM:D2_CLK:TO:FFS:TIG:./xilinx_pcie_2_0_ep_v6_map.map- No TNM, TPSYNC or user group named "D2_CLK" is defined../xilinx_pcie_2_0_ep_v6_map.map-ERROR:TSDatabase:19 - Processing TIMESPEC definition./xilinx_pcie_2_0_ep_v6_map.map: TS_J2_TO_D2=FROM:FFS:TO:D2_CLK:TIG:./xilinx_pcie_2_0_ep_v6_map.map- No TNM, TPSYNC or user group named "D2_CLK" is defined../xilinx_pcie_2_0_ep_v6_map.map-ERROR:TSDatabase:19 - Processing TIMESPEC definition./xilinx_pcie_2_0_ep_v6_map.map- TS_J3_TO_D2=FROM:FFS:TO:D2_CLK:TIG:--./xilinx_pcie_2_0_ep_v6_map.mrp- TS_D2_TO_T2=FROM:D2_CLK:TO:FFS:TIG:./xilinx_pcie_2_0_ep_v6_map.mrp- No TNM, TPSYNC or user group named "D2_CLK" is defined../xilinx_pcie_2_0_ep_v6_map.mrp-ERROR:TSDatabase:19 - Processing TIMESPEC definition./xilinx_pcie_2_0_ep_v6_map.mrp: TS_J2_TO_D2=FROM:FFS:TO:D2_CLK:TIG:./xilinx_pcie_2_0_ep_v6_map.mrp- No TNM, TPSYNC or user group named "D2_CLK" is defined../xilinx_pcie_2_0_ep_v6_map.mrp-ERROR:TSDatabase:19 - Processing TIMESPEC definition./xilinx_pcie_2_0_ep_v6_map.mrp- TS_J3_TO_D2=FROM:FFS:TO:D2_CLK:TIG:$