我在某处读到前10个MAP成本表提供了最广泛的变化算法,而剩下的90个是它们的微妙变化。我的设计非常复杂(如下所述),我在过去的会议时间里取得了很大的成功
通过改变CT来实现。
但是,在为设计添加另一个DSP路径(与先前使用的路径相同)之后,我无法满足前10个CT的任何时序。
然而,其中一些非常接近。
我正在寻找的是,如果有人知道更多关于成本表的信息。
进一步来说:
1)我在第一句中所作的陈述是真的吗?
2)如果是这样,90个变体中的哪一个对应于CT2?
设计细节:
* Virtex 6 - SX475(最大可用)
*设计中至少30个时钟域(BUFG / BUFR)
*使用系统生成器创建的DSP子系统
* 16驱动器SATA RAID子系统
* QDR子系统(Xilinx核心)
* PlanAhead用于从多个单独的网表中实现设计
*为DSP和RAID子系统生成的分区,以便在实现定时时锁定路由
以上来自于谷歌翻译
以下为原文
I read somewhere that the first 10 MAP cost tables provide the most widely varying placement algorithm, while the remaining 90 are subtle varia
tions on them. My design is extremely complex (described below), and I've had a lot of success in the past meeting timing by varying the CT's. However, after adding another DSP path (which is identical to a previously used path) to the design, I'm not able to meet timing with any of the first 10 CT's. A few of them are very close, however. What I'm looking for is if anybody knows more information about the cost tables. More specifically:
1) Is the statement I made in the first sentence true?
2) If so, which of the 90 variations correspond to CT2?
Design details:
* Virtex 6 - SX475 (largest available)
* At least 30 clock domains in the design (BUFG/BUFR)
* DSP subsystem created with system generator
* 16 drive SATA RAID subsystem
* QDR subsystem (Xilinx Core)
* PlanAhead used to implement design from a number of individual netlists
* Partitions generated for DSP and RAID subsystems to allow locking down routing when timing achieved