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杨帆

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[问答]

总线宏和信号修整出现错误

我正在开发一个部分重新配置的项目,它使用总线宏(我知道它们已被弃用;但它是项目使用的内容并且更改会使项目陷入困境)。
问题是
如果总线宏没有连接任何输出,则ISE Map(12.1)会抛出错误。
ISE无法识别信号的“保存”属性(属性s:字符串; dummy_output的属性:信号为“是”;)
我已尝试使用AR#30112中建议的解决方案但没有成功(也许我没有正确解释)。
是否有任何解决方案不涉及禁用“修剪未使用的逻辑”,也不添加大量的虚拟逻辑和输出信号?

以上来自于谷歌翻译


以下为原文

I'm working on a project on partial reconfiguration which uses bus macros (I know they're deprecated; but it's what the project uses and changing that would mess up the project too much).

The problem is that
  • If a bus macro doesn't have any output connected, ISE Map (12.1) throws an error.
  • ISE doesn't recognize "save" attributes for signals (attribute s: string; attribute s of dummy_output: signal is "yes"; )
I have tried with the solution suggested in AR #30112 with no success (maybe I haven't interpreted it right).

Is there any solution that does not involve disabling "trim unused logic" nor adding lots of dummy logic and output signals?

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李富才

2018-10-8 11:34:09
尝试使用UCF Save属性:
NET“net_name”S;
在原帖中查看解决方案

以上来自于谷歌翻译


以下为原文

Try it with a UCF Save property:
NET "net_name" S;
View solution in original post
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洪茗苞

2018-10-8 11:48:54
您可以尝试在MAP中使用“-u”选项。
它指示MAO不删除未使用的逻辑

以上来自于谷歌翻译


以下为原文

You could try using the "-u" option in MAP. It instructs MAO to not remove unused logic
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李富才

2018-10-8 11:58:33
我不熟悉PR流程但不是Bus Macros硬宏(.nmc文件)?
在那种情况下,硬宏中的任何东西都不会被修剪掉。
你是否有连接宏的网络修剪问题?
你看到什么错误?
如果您让我们更深入地了解故障模式,那将会有很大帮助。

以上来自于谷歌翻译


以下为原文

I'm not that familiar with the PR flow but aren't Bus Macros hard macros (.nmc files)? In that case nothing in a hard macro ever gets trimmed. Are you having a trimming problem with a net connected to the macro? What error are you seeing? It would help a lot if you gave us more insight into the failure mode.
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陈英

2018-10-8 12:06:11
shantesh:使用-u的问题是我不想在_all_我的设计中禁用逻辑修整,只在那些特定部分中。
但无论如何,谢谢;
这是我已经考虑过(和丢弃)的可能性。
bwade:这不是硬宏上的网络被修剪的;
它是连接硬宏输出的网络(并且没有连接到任何其他东西)正在被修剪。
自从我改变设计以来,我不确定具体的错误信息;
我认为就是这个(来自AR#30112):
“ERROR:Pack:1195  -  Symbol”“没有输出引脚连接。”
(作为公交车宏)。
也就是说,Xilinx修剪了未连接的输出网络,然后抱怨没有任何输出的元素。
我现在正在使用的解决方法(似乎有效)正在为这些元素制作一些“虚拟逻辑”(将其中一个输出连接到另一个输入或输出引脚)。
尽管它以不必要的逻辑填充了设计,但它仍然有用。

以上来自于谷歌翻译


以下为原文

shantesh: The problem with using -u is that I don't want to disable logic trimming in _all_ my design, only in those specific parts. But thanks anyway; it's a possibility I have already considered (and discarded).
 
bwade: It's not the nets on the hard macro itself being trimmed; it's the nets to which the hard macro outputs are connected (and which aren't connected to anything else) which is getting trimmed.
 
I'm not sure about the specific error message since I changed the design; I think it's this one (from AR #30112):
"ERROR:Pack:1195 - Symbol "" has no output pin connections." ( being the bus macro).
This is, Xilinx trims the unconnected output nets and then complains about the element not having any output.
 
The workaround I'm using right now (and which seems to work) is making some "dummy logic" for those elements (connecting one of their outputs to another input or to an output pin). It serves its purpose, although it fills the design with unnecessary logic.
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