shantesh:使用-u的问题是我不想在_all_我的设计中禁用逻辑修整,只在那些特定部分中。
但无论如何,谢谢;
这是我已经考虑过(和丢弃)的可能性。
bwade:这不是硬宏上的网络被修剪的;
它是连接硬宏输出的网络(并且没有连接到任何其他东西)正在被修剪。
自从我改变设计以来,我不确定具体的错误信息;
我认为就是这个(来自AR#30112):
“ERROR:Pack:1195 - Symbol”“没有输出引脚连接。”
(作为公交车宏)。
也就是说,Xilinx修剪了未连接的输出网络,然后抱怨没有任何输出的元素。
我现在正在使用的解决方法(似乎有效)正在为这些元素制作一些“虚拟逻辑”(将其中一个输出连接到另一个输入或输出引脚)。
尽管它以不必要的逻辑填充了设计,但它仍然有用。
以上来自于谷歌翻译
以下为原文
shantesh: The problem with using -u is that I don't want to disable logic trimming in _all_ my design, only in those specific parts. But thanks anyway; it's a possibility I have already considered (and discarded).
bwade: It's not the nets on the hard macro itself being trimmed; it's the nets to which the hard macro outputs are connected (and which aren't connected to anything else) which is getting trimmed.
I'm not sure about the specific error message since I changed the design; I think it's this one (from AR #30112):
"ERROR:Pack:1195 - Symbol "
" has no output pin connections." ( being the bus macro).
This is, Xilinx trims the unconnected output nets and then complains about the element not having any output.
The workaround I'm using right now (and which seems to work) is making some "dummy logic" for those elements (connecting one of their outputs to another input or to an output pin). It serves its purpose, although it fills the design with unnecessary logic.
shantesh:使用-u的问题是我不想在_all_我的设计中禁用逻辑修整,只在那些特定部分中。
但无论如何,谢谢;
这是我已经考虑过(和丢弃)的可能性。
bwade:这不是硬宏上的网络被修剪的;
它是连接硬宏输出的网络(并且没有连接到任何其他东西)正在被修剪。
自从我改变设计以来,我不确定具体的错误信息;
我认为就是这个(来自AR#30112):
“ERROR:Pack:1195 - Symbol”“没有输出引脚连接。”
(作为公交车宏)。
也就是说,Xilinx修剪了未连接的输出网络,然后抱怨没有任何输出的元素。
我现在正在使用的解决方法(似乎有效)正在为这些元素制作一些“虚拟逻辑”(将其中一个输出连接到另一个输入或输出引脚)。
尽管它以不必要的逻辑填充了设计,但它仍然有用。
以上来自于谷歌翻译
以下为原文
shantesh: The problem with using -u is that I don't want to disable logic trimming in _all_ my design, only in those specific parts. But thanks anyway; it's a possibility I have already considered (and discarded).
bwade: It's not the nets on the hard macro itself being trimmed; it's the nets to which the hard macro outputs are connected (and which aren't connected to anything else) which is getting trimmed.
I'm not sure about the specific error message since I changed the design; I think it's this one (from AR #30112):
"ERROR:Pack:1195 - Symbol "
" has no output pin connections." ( being the bus macro).
This is, Xilinx trims the unconnected output nets and then complains about the element not having any output.
The workaround I'm using right now (and which seems to work) is making some "dummy logic" for those elements (connecting one of their outputs to another input or to an output pin). It serves its purpose, although it fills the design with unnecessary logic.
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