嘿，正如标题所暗示的，我的PIC18F44 20 I2C主机总是接收ACK，即使SDA线是打开的（不包括上拉电阻）。检查波形：图1：一个地址传输与SDA上的唯一连接是4.7K拉出。数据表说，ACK位应该在第九SCL高时间采样，在下降沿后保持一个小的时间。这里的保持时间大约是8US，而数据表不要求最大的100kHz和0.9MSMAX为400 kHz模式。图2：第九SCL的下降沿与SDACLARED SDA的下降沿是高的，但是在SSPCON2中的AkStAT位被清除。如果我没有从奴隶那里接收数据，主人是否应该在第八SCL之后声明SDA？当连接到一个从属设备并且地址匹配发生时，一切似乎都正常。目前正在初始化：SSPSTAT＝0x00 SSPCON1= 0x28 SSPCON2= 0x00 SCL运行在25KHZONE思想？谢谢。编辑：0.9US -0.9MS的400 kHz保持时间
以上来自于百度翻译
以下为原文
Hey all, as the
title suggests, my PIC18F4420 I2C master is always receiving an ACK even if the SDA line is open (not including the pullup resistor). Check out the waveform:
Fig 1: One address transmission with the only connection on SDA being a 4.7k pullup.
The datasheet says the ACK bit should be sampled during the 9th SCL high time with a small hold time after the falling edge. Here the hold time is around 8us while the datasheet claims no max for 100kHz and 0.9ms max for 400kHz mode.
Fig 2: Falling edge of 9th SCL related to falling edge of SDA
Clearly SDA is high, yet the ACKSTAT bit in SSPCON2 is cleared. Should the master even be asserting SDA after the 8th SCL if I am not receiving data from a slave?
When a slave is connected and an address match occurs everything SEEMS to work okay.
Currently for initialization:
SSPSTAT = 0x00
SSPCON1 = 0x28
SSPCON2 = 0x00
SCL running at 25kHz
Any ideas? Thanks.
Edit: 0.9us -> 0.9ms for 400kHz hold time
Attached Image(s)
举报
