亲爱的,
流水线SRAM的数据表(例如部分CY7C1382KV33)在第8页的“单读访问”段落中表示,支持连续的读周期。一个读周期有一个延迟2个时钟周期。
这是否意味着你可以每2个CLK周期做一个读周期,或者你可以在每个CLK周期启动一个读周期吗?
谢谢和问候,
托马
以上来自于百度翻译
以下为原文
Dear,
The datasheet of a pipelined SRAM (for example part CY7C1382KV33) states in the "Single Read Accesses" paragraph on page 8, that Consecu
tive read cycles are supported. One single read cycle has a lantency of 2 Clk cycles.
Does this mean you can do a read cycle every 2 Clk cycles, or can you initiate a read cycle every Clk cycle?
Thanks and best regards,
Toma