引用: Evawang 发表于 2018-8-14 07:42
TM4C123x 的PD7和PF0默认为NMI功能。
这些管脚在进行功能设置前需要解锁。例如对PD7:
HWREG(GPIO_PORTD_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;
把GPIO解锁的逻辑贴出来吧,对照Datasheet和寄存器一看就明白了:
9.2.4 Commit Control
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is provided for the GPIO pins that can be used as the four
JTAG/SWD pins (PC[3:0])and the NMI pin (PD7 and PF0). Writes to protected bits of the GPIO
Alternate Function Select (GPIOAFSEL) register (see page 589), GPIO Pull Up Select (GPIOPUR)
register (see page 595), GPIO Pull-Down Select (GPIOPDR) register (see page 597), and GPIO
Digital Enable (GPIODEN) register (see page 600) are not committed to storage unless the GPIO
Lock (GPIOLOCK) register (see page 602) has been unlocked and the appropriate bits of the GPIO
Commit (GPIOCR) register (see page 603) have been set.
引用: Evawang 发表于 2018-8-14 07:42
TM4C123x 的PD7和PF0默认为NMI功能。
这些管脚在进行功能设置前需要解锁。例如对PD7:
HWREG(GPIO_PORTD_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;
把GPIO解锁的逻辑贴出来吧,对照Datasheet和寄存器一看就明白了:
9.2.4 Commit Control
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is provided for the GPIO pins that can be used as the four
JTAG/SWD pins (PC[3:0])and the NMI pin (PD7 and PF0). Writes to protected bits of the GPIO
Alternate Function Select (GPIOAFSEL) register (see page 589), GPIO Pull Up Select (GPIOPUR)
register (see page 595), GPIO Pull-Down Select (GPIOPDR) register (see page 597), and GPIO
Digital Enable (GPIODEN) register (see page 600) are not committed to storage unless the GPIO
Lock (GPIOLOCK) register (see page 602) has been unlocked and the appropriate bits of the GPIO
Commit (GPIOCR) register (see page 603) have been set.
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