pxa255开发板原理图及源代码

pxa255开发板原理图,包括源代码
pxa255 pdf
【例5.4】用initial 过程语句对测试变量A、B、C 赋值
`timescale 1ns/1ns
module test;
reg A,B,C;
initial
begin
A = 0; B = 1; C = 0;
#50 A = 1; B = 0;
#50 A = 0; C = 1;
#50 B = 1;
#50 B = 0; C = 0;
#50 $finish ;
end
endmodule
【例5.5】用begin-end 串行块产生信号波形
`timescale 10ns/1ns
module wave1;
reg wave;
parameter cycle=10;
initial
begin
王金明：《Verilog HDL 程序设计教程》
- 5 -
wave=0;
#(cycle/2) wave=1;
#(cycle/2) wave=0;
#(cycle/2) wave=1;
#(cycle/2) wave=0;
#(cycle/2) wave=1;
#(cycle/2) $finish ;
end
initial $monitor($time,,,"wave=%b",wave);
endmodule