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S5PV210的数据手册介绍中断体系比较简洁：
1.1 OVERVIEW OF VECTORED INTERRUPT CONTROLLER
The interrupt controller in S5PV210 is composed of four Vectored Interrupt Controller (VIC), ARM PrimeCell
PL192 and four TrustZone Interrupt Controller (TZIC), SP890.
Four TZIC’s and four VIC’s are daisy-chained to support up to 93 interrupt sources. The TZIC provides a software
interface to the secure interrupt system in a TrustZone design. It provides secure control of the nFIQ interrupt and
masks the interrupt source(s) from the interrupt controller on the non-secure side of the system (VIC). Use the
latter to generate nIRQ signal.
To generate nFIQ from the non-secure interrupt sources, the TZIC0 takes the nNSFIQIN signal from the nonsecure interrupt controller.
1.1.1 KEY FEATURES OF VECTORED INTERRUPT CONTROLLER
• Supports 93 vectored IRQ interrupts
• Fixed hardware interrupts priority levels
• Programmable interrupt priority levels
• Supports Hardware interrupt priority level masking
• Programmable interrupt priority level masking
• Generates IRQ and FIQ
• Generates Software interrupt
• Test registers
• Raw interrupt status
• Interrupt request status
• Supports Privileged mode for restricted access
所以要想使用其中断，直接去浏览寄存器也是可以的，在这里就不一一介绍寄存器。本杰提供的代码有参考别人带代码。
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