VHDL GPS守时

GPS守时程序如下：

LIBRARY ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
USE ieee.std_logic_arith.all;
ENtiTY RTL IS
PORT
(CLK :IN STD_LOGIC;
  PPS:IN STD_LOGIC;
  OBEYPPS:OUT STD_LOGIC
);
END RTL;
ARCHITECTURE BEHAVE OF RTL IS
CONSTANT StandFreq: STD_LOGIC_VECTOR(26 DOWNTO 0):= "101111101011110000011111111";--- 100M-1
CONSTANT COUNT_ZERO: STD_LOGIC_VECTOR(26  DOWNTO 0) :="000000000000000000000000000";
CONSTANT StandPPSWidth:STD_LOGIC_VECTOR(26  DOWNTO 0):="001001100010010110100000000";---200MS
SHARED VARIABLE COUNT_2S: STD_LOGIC_VECTOR(26  DOWNTO 0):="000000000000000000000000000";
SIGNAL CLR: STD_LOGIC;
SIGNAL CLR1 : STD_LOGIC;
SIGNAL SEC: STD_LOGIC:='0';
BEGIN
PROCESS(CLK,PPS)
BEGIN
IF(CLK'EVENT AND CLK='1') then
  CLR<=PPS;
  CLR1<=CLR;
END IF;

END PROCESS;
PROCESS(CLK)---generated the obey pps and win2,NormalPPSFlag
BEGIN
IF CLK'EVENT AND  CLK='1' THEN
  IF CLR = '1' AND CLR1 = '0'  THEN
   COUNT_2S := (OTHERS =>'0'); -------- 清零
  END IF;
  IF COUNT_2S=COUNT_ZERO THEN
    SEC <='1';
  ELSIF  COUNT_2S =StandPPSWidth THEN
   SEC <='0';
  END IF;
  IF COUNT_2S    COUNT_2S:= COUNT_2S + 1 ;
  ELSE
   COUNT_2S:= (OTHERS =>'0'); -------- 清零
  END IF;
END IF;
END PROCESS;
OBEYPPS<=SEC;
END  BEHAVE;
程序实现的功能是：有pps的时候，pps实时校正SEC，没有PPS时，通过晶振自己守时产生SEC。晶振采用的是铷钟，很精确。
程序运行出现的状况：有PPS时SEC输出很准确，没有pps时，自己产生的SEC一直漂 ，一天有5Us的漂浮。
漂浮现象是：先慢慢右移，右移300ns后，大幅度左移，到刚才偏右位置。
为什么出现这种现象？

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