UART3中的Modbus串行通信错误是什么原因造成的？

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我尝试实现 modbus RTU 主站，但有一个问题，即当有许多数据要写入从站时，从站收到一个分成多个数据包的数据包。例如，如果一个写入多个保持寄存器包(FC:03, Addr:0, Num:100) 被发送到slave 那么下面的数据将被接收到slave 并且slave 在正常情况下发送响应。
[size=\"2\"][color=\"#000000\"]接收：002192-01 10 00 00 00 64 C8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D4 93
[size=\"2\"] Tx：002193-01 10 00 00 00 64 C1 E2
但是，slave 有时会收到如下从一个数据包中分割出来的多个数据包。因为slave收到了异常的包，所以没有给master发送响应。
[size=\"2\"]接收： 002256-01 10 00 00 00
[size=\"2\"]接收： 002257-64 C8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Rx：002258-00 00 00 00 00 00 00 00
[size=\"2\"]00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D4 93
奇怪的是，这个问题在所有波特率的 UART1 中都没有发生。与 UART1 不同，UART 3 有这个问题，但在 115200bps 波特率设置下没有这个问题。鉴于此症状，我认为时钟设置不正确。请给我一些关于这个问题的建议。
为了只看到这个问题，我使用了SDK中的ipuart_interrupt_rb_transfer示例工程，修改为发送一个写入多个寄存器的数据包。