[问答]

RCC在165 MHz时的STM32H7硬故障怎么解决？

120 RCC

问答对人有帮助，内容完整，我也想知道答案 0 我有 STM32H7B3I-DK（MCU：STM32H7B3LIH6Q），我试图通过 PLL 运行 HSI 或 HSE 使 sys_ck 接近其最大频率 280 MHz。问题是我最多只能达到 164 MHz。再高一点，我就会犯一个严重的错误。有什么我忘记或搞砸了吗？代码： File : main.c Purpose : Generic application start / #include #include #include void setup_user_leds(void); void user_led_red_high(void); void user_led_red_low(void); void user_led_blue_low(void); void user_led_blue_high(void); //User LEDs are on PG2 and PG11 void setup_user_leds(void) { uint32_t reg_copy; //enable the clock to GPIOG peripheral RCC->AHB4ENR \|= RCC_AHB4ENR_GPIOGEN; //(MODER states are 2 bits, hence Read/Modify/Write) //make a copy of the current state of the register reg_copy = GPIOG->MODER; //use the masks to clear the bits reg_copy &= ~(GPIO_MODER_MODE2_Msk\|GPIO_MODER_MODE11_Msk); //set any of the cleared bits reg_copy \|= (GPIO_MODER_MODE2_0\|GPIO_MODER_MODE11_0); //save it back to memory GPIOG->MODER = reg_copy; } void user_led_red_high(void) { GPIOG->BSRR = GPIO_BSRR_BS2; } void user_led_red_low(void) { GPIOG->BSRR = GPIO_BSRR_BR2; } void user_led_blue_low(void) { GPIOG->BSRR = GPIO_BSRR_BR11; } void user_led_blue_high(void) { GPIOG->BSRR = GPIO_BSRR_BS11; } void delay() { uint64_t t,i; t = 1000000; for(i=0;i { __NOP(); } } void set_system_clk_hse(int pre_speed, int divisor) { if (280 < pre_speed \|\| pre_speed < 64) return; // VCO output range F_ref[64, 280] (F_ref = 2) must be respected if (64 < divisor \|\| divisor < 1) return; RCC -> CFGR \|= RCC_CFGR_SW_PLL1; // System clock and trace clock switch: Select PLL1 as system clock //while ((RCC -> CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL1); // System clock switch status: Wait until PLL1 is system clock RCC -> CR \|= RCC_CR_HSEON; // HSE clock enable while (!(RCC -> CR & RCC_CR_HSERDY)); // Wait until HSE clock is ready RCC -> PLLCKSELR = 0x020200C2; // Divide HSE by 12 = 24 / 12 = 2 MHz = F_ref int divp = 2divisor - 1; int divn = pre_speed - 1; RCC -> PLL1DIVR = 0x01010000 + (divp << RCC_PLL1DIVR_P1_Pos) + divn; // Set register (reset = 0x01010280) RCC -> CR \|= RCC_CR_PLL1ON; // PLL1 enable //while((RCC -> CR & RCC_CR_PLL1RDY) == 0); // Wait until PLL1 clock is ready } void set_system_clk_hsi(int pre_speed, int divisor) { if (280 < pre_speed \|\| pre_speed < 64) return; // VCO output range F_ref[64, 280] (F_ref = 2) must be respected if (64 < divisor \|\| divisor < 1) return; RCC -> CFGR \|= RCC_CFGR_SW_PLL1; // System clock and trace clock switch: Select PLL1 as system clock //while ((RCC -> CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL1); // System clock switch status: Wait until PLL1 is system clock int divp = 2divisor - 1; int divn = pre_speed - 1; RCC -> PLL1DIVR = 0x01010000 + (divp << RCC_PLL1DIVR_P1_Pos) + divn; // Set register (reset = 0x01010280) RCC -> CR \|= RCC_CR_PLL1ON; // PLL1 enable //while((RCC -> CR & RCC_CR_PLL1RDY) == 0); // Wait until PLL1 clock is ready } /******************************************************************** * * main() * * Function description * Application entry point. / int main(void) { int pre_speed = 165; // Theoretically, pre_speeds from 64 to 280 should work int divisor = 1; // [1, 64] set_system_clk_hsi(pre_speed, divisor); // Speed = pre_speed / divisor; trial max ~ 164 MHz, theoretical max = 280 MHz (high range) or 210 MHz (low range) / frequency: before divn1 = 2 after divn1 = 2 * speed after div[p/q/r]1 = speed */ setup_user_leds(); while(1) { user_led_red_high(); delay(); user_led_blue_high(); delay(); user_led_red_low(); delay(); user_led_blue_low(); delay(); } } 0
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答案对人有帮助，有参考价值 0 您不应该在实际设置 PLL 之前*将 PLL 设置为系统时钟源。此外，确保为给定的系统时钟频率设置了正确的 VOS 和 FLASH 延迟。

2023-1-3 11:38:03 评论举报陈霞