将Atlys-VMODCam参考设计导入Nexys 3需要考虑什么？

您好专家，大师和社区成员，
显然正在通过这个论坛显示到目前为止还没有人将Atlys VMODCam参考设计移植到Nexys 3，所以我想要求提供一个通用指南，让新手和中级用户不那么痛苦。
在我的建议中，例如：
1. Atlys参考设计使用某种类型的DDR2 RAM（由MIG生成的接口）来缓冲来自VMODCam的视频数据，是否可以按原样使用，但当然分别改变UCF文件中的引脚分配？
或者Nexys 3的CellRAM / PCM / SPI RAM可以直接访问和连接？
2. Atlys参考设计使用中央模块进行总时钟管理。
它是如何工作和与单个模块交互的？
它可以直接移植还是需要通过Clocking向导重新创建？
在为Nexys3执行此步骤时要记住的任何约束或建议？
3. Atlys参考设计使用DVI视频输出格式。
并且由于Nexys 3不支持它，但是VGA然后在从内存帧缓冲区获取VGA输出时要考虑什么（如第1点所述）？
4.还有其他建议和指导吗？
祝大家早上好。
- 来自DE的问候



以下为原文

Hello Experts, Gurus and Community Members,
As apparently going through this forum shows that nobody so far has succedded in porting the Atlys VMODCam reference design to Nexys 3, so I would like to request that a general guideline be provided for making such thing less painful for newbies and intermediate users.
In my suggestion, for example:
1. Atlys reference design uses a certain type of DDR2 RAM (it's interface generated by MIG) for buffering the video data from VMODCam, can it be used as it is, but of course changing the pin assignments in UCF file respectively? Or CellRAM/PCM/SPI RAM of Nexys 3 be accessed and interfaced with directly?
2. Atlys reference design uses a central module for total clock managment. How is it working and interacting with individual modules? Can it be ported directly or it also needs to be re-created via Clocking wizard? Any constraints or suggestions to keep in mind while doing this step for Nexys3?
3. Atlys reference design uses a DVI video output format. And since Nexys 3 has no support for it but VGA then what to consider while making the VGA output to be taken from the memory frame buffer (as mentioned in point 1.)?
4. Any other suggestions and guidlines?

Have a great morning.
--greetings from DE