完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
扫一扫,分享给好友
您好,我使用的PIC18F23 K22似乎是由一个时钟周期过度移位的数据由SPI主机发送。我已经将一个逻辑分析器连接到SPI总线,并确认在SPI模式下的FT232H在时钟的下降沿上正确地发送数据,并且正确地对SPI总线计时一个字节的适当次数。从我观察到的SPI大师没有任何额外的时钟转换。我在时钟线上安装了示波器,我也没有在时钟线上发现任何毛病。为了帮助解决高速故障的可能性,我在时钟总线上安装了一个内线电阻,它也起到了阻尼边缘振铃的良好效果。然而,作为PIC18F23 K22的SPI从机左移所有接收比特1。如果0x46被发送到从站,从站保存0x8C,如果0x8C被发送,从站保存0x0C,最后如果0x1F被发送,从站保存0x3F。我试过同一系列的不同芯片,但问题是一致的。我已经没有办法解决这个问题了。有什么想法吗?非常感谢。-PIC18F23k22PLLCFG=OFF,PRICLKEN=ON,FCMEN=ON,FCMEN=OFF,IESO=OFF,FOSC=IESO=OFF,FOSC=HSMPBORE=OFF,IESO=OFOFOFOFOFF,IESO=OFOFF=OFF,BORV=220,PWRTEN=ONWRTEN=ONWWWRTEN=ONWWDTEN=OFFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOFOF描述:SPI主机-FT232H bre从Ada.itSPI从属中退出-启用了PIC18F23K22 w/~CS。时钟极性-空闲低,有源高时钟速度-500KHz/2us周期数据输出-MSSP初始化代码段的上升边码配置
以上来自于百度翻译 以下为原文 Hello, The PIC18F23K22 I am using appears to be over-shifting by one clock cycle the data being transmitted by the SPI master. I have attached a logic analyzer to the SPI bus and confirmed that my FT232H in SPI mode is correctly sending data on the falling edge of the clock and is correctly clocking the SPI bus the proper amount of times for one byte. There isn't any extra clock transitions from the SPI Master that I have observed. I attached an oscilloscope to the clock line and I didn't observe any glitches on the clock line either. To help with the possibility of high speed glitches I put an inline resistor on my clock bus, it also had a nice affect of damping the edge ringing. However, the SPI Slave which is a PIC18F23K22 is left shifting all received bits by 1. If 0x46 is sent to the slave, the slave saves it 0x8C, if 0x8C is sent the slave saves 0x0C and finally if 0x1F is sent the slave saves 0x3F. The SPI clock speed is 500KHz and I do not think that my breadboard contributes enough noise to be a factor in this issue. I tried a different chip of the same series and the problem is consistent. I have run out of ideas on how to resolve this problem. Any ideas? Much Thanks. -R The configuration of the PIC18F23k22 PLLCFG=OFF, PRICLKEN=ON, FCMEN=OFF, IESO=OFF, FOSC=HSMP BOREN=OFF, BORV=220, PWRTEN=ON WDTPS=16384, WDTEN=OFF HFOFST=OFF, PBADEN=OFF, MCLRE=EXTMCLR STVREN=OFF, DEBUG=OFF, LVP=ON, XINST=OFF Fosc = 11.0592MHz Summary of Configuration: SPI Master - FT232H breakout from AdaFruit SPI Slave - PIC18F23K22 w/ ~CS enabled. Clock Polarity - Idle Low, Active High Clock Speed - 500KHz / 2 us period Data Out - Falling Edge Data In - Rising Edge Code Config of the MSSP MSSP Initialization Code snip SSP1CON1bits.SSPM = 0x4; SSP1CON1bits.CKP = 0; //clock idle state SSP1STATbits.CKE = 0; //data valid position SSP1STATbits.SMP = 0; TRISCbits.TRISC3 = 1; //SCL1 TRISCbits.TRISC4 = 1; // SPI1-DI TRISAbits.TRISA5 = 1; //~SS1 |
|
相关推荐
4个回答
|
|
不要设置DEBUG配置位-留下IDE来做。我不确定你的注释“Data in-Ri.edge”指的是什么,但是SMP设置0将使PIC18F23k22样本位于时钟的下降沿。也请向我们展示你完整的ACTUAL代码-它使帮助你变得如此容易。Su存储区域网络
以上来自于百度翻译 以下为原文 Don't set the DEBUG config bit - leave the IDE to do that. I'm not sure what your comment 'Data in - Rising edge' refers to but the SMP setting of 0 will make the PIC18F23k22 sample on the falling edge of the clock. Also please show us your complete ACTUAL code - it makes helping you so much easier. Susan |
|
|
|
当PIC被用作从属设备时,SMP需要被设置为每数据表0。我可能会弄错了,当图片将从总线上采样数据时,图15-10建议CKE必须是1,这样图片才能在上升沿上采样。我把它设定为0。这可能是个问题。在这种情况下,完整的源代码是无济于事的。我所展示的是如何配置MSSP,除了关于何时从总线上采样数据的问题,其他一切都正常。我做了更多的搜索,发现PIC18F450有同样的问题。我看了看那部分的勘误表,发现第37项,上面说给从pic的SDI线路加一个电阻解决了问题。它不是具体的价值,它鼓励实验(认真看看它)。好,低电平,这解决了我的问题。所以这里的解决方案是在从主SDO线到从SDI线的数据路径中添加一个电阻。在我的情况下,一个1K欧姆电阻工作。我的所有问题都是纯硬件。谢谢你给我一个问题的思考。- R.
以上来自于百度翻译 以下为原文 SMP needs to be set to 0 per the datasheet when the pic is being used as a slave device. I could be mistaken on when the pic will sample the data off the bus, figure 15-10 suggests that CKE needs to be 1 for the pic to sample on the rising edge. I have it set to 0. That could be a problem. The full source code won't help in this case. What I show is how the MSSP is configured, aside from the question about when the pic samples the data off the bus everything else is in order. I did some more searching around noticed that the pic18f4550 had the same problem. I looked at the errata for that part and found item 37, which said that putting a resistor on the SDI line of the slave pic resolved the problem. It wasn't specific on the value and it encouraged experimentation(seriously take a look at it). Well low and behold that resolved my problem here. So the solution here is to add a resistor in the data path from the Master SDO line to the slave SDI line. In my case a 1K ohm resistor worked. All in all my issues were purely hardware. Thank you for giving a thought to my problem. -R. |
|
|
|
PIC可能没有使用YouTFT22H的相同SPI模式(您错过MSB,因为您在错误的时间上获得数据位尊重时钟)。根据您分配给CKE和CKP的值,有4种可能的SPI协议模式。尝试改变这些值。建议:设计人员审查SPI从数据表来确定SPI模式的实现。FTMI设备只能支持MPSE引擎限制的模式0和模式2。“这里:HTTPS://E.WiKiTo.Org/Wiki/SerialPypeRiFalalIdFieldFieleBo.x模型,0是CKP=0,CKE=1模式2是CKP=1,CKE= 0,使用CKE=0,CKP=0,即模式1。
以上来自于百度翻译 以下为原文 Probably the PIC is not using the same SPI mode of your FT232H (you miss MSB because you get data bit on the wrong time respect the clock). There are 4 possible mode for SPI protocol, depending by the values you assign to CKE and CKP. Try to change that values. Here: http://www.ftdichip.com/Support/Documents/AppNotes/AN_114_FTDI_Hi_Speed_USB_To_SPI_Example.pdf "It is recommended that designers review the SPI Slave data sheet to determine the SPI mode implementation.FTDI device can only support mode 0 and mode 2 due to the limitation of MPSSE engine." And here: https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus#Mode_numbers On PIC, mode 0 is CKP = 0 and CKE = 1 mode 2 is CKP = 1 and CKE = 0 you are using CKE = 0 and CKP = 0, that's mode 1. |
|
|
|
Jarni,我已经解决了这个问题,通过在PIC和FT32H芯片之间放置一个与MISO信号内嵌电阻器。正如我在前一篇文章中所指出的,这是在PIC18F450中发现的类似问题。我目前的SPI设置没有任何负面影响,而且它们对我的应用程序看起来是正确的。我看到的具体问题是接收缓冲区的过度移位。对于给定的8位传输,图片上的接收缓冲区将移位9次,最后一个位将是之前接收的位的副本。
以上来自于百度翻译 以下为原文 Jarni, I have resolved the issue by placing a resistor inline with MISO signal between the pic and the FT232H chip. As I indicated in my previous post, this was a similar issue found in the pic18F4550. I haven't had any adverse effects with my current SPI settings and they appear to be correct for my application. The specific problem I was seeing was an over shift of the receive buffer. For a given 8 bit transfer the receive buffer on the pic would shift 9 times and the last bit would be a copy of the bit that was received before. |
|
|
|
只有小组成员才能发言,加入小组>>
5189 浏览 9 评论
2009 浏览 8 评论
1933 浏览 10 评论
请问是否能把一个ADC值转换成两个字节用来设置PWM占空比?
3181 浏览 3 评论
请问电源和晶体值之间有什么关系吗?PIC在正常条件下运行4MHz需要多少电压?
2232 浏览 5 评论
746浏览 1评论
632浏览 1评论
有偿咨询,关于MPLAB X IPE烧录PIC32MX所遇到的问题
517浏览 1评论
PIC Kit3出现目标设备ID(00000000)与预期的设备ID(02c20000)不匹配。是什么原因
644浏览 0评论
544浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-12-1 05:16 , Processed in 1.206579 second(s), Total 83, Slave 67 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号