怎么驱动多个缓冲区？

嗨，
我不确定你的设计要求。
但是从帖子中我了解到你需要一个如下界面：
clk_p-- | -------- -------- IBUFGDS | --MIG
clk_n-- |
|  - 时钟精灵
如前所述，错误是由于级联ibuf。
MIG和时钟向导内部有IBUF，并提出问题。
您可以通过以下选项在时钟向导中禁用此输入缓冲区：
如上所示，您需要通过为时钟输入选择“No buffer”来重新设置cloking向导核心。
对于MIG，我不认为可以选择禁用这样的缓冲区。
在这种情况下，您需要编辑MIG生成的infrastructure.v文件并注释IBUFG / IBUFGDS并保存。
我做了以上修改，现在设计通过翻译阶段。
请检查附件项目。
还要重新检查它是否符合您的设计需求。
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
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在原帖中查看解决方案
top1.zip 3159 KB



以下为原文

Hi,
 
I am not sure of your design requirements. But from the posts I understood that you need an interface as below:
 
clk_p--|--------IBUFGDS--------|--MIG
clk_n--|                                       |--clocking wizard
 
As already mentioned the error is due to cascading ibuf. The MIG and clocking wizard internally have IBUF in them and cauing the issue. You can disable this input buffer in clocking wizard by the below option:
 

 
You need to regernate the cloking wizard core by selecting "No buffer" for clock input as shown above.
 
For MIG I dont think there is option to disable buffers like this. In this case you need to edit the MIG generated infrastructure.v file and comment the IBUFG/IBUFGDS and save it. 
 
I made the above changes, now the design passes translate phase. Please check the attached project. Also recheck if it meets your design needs.
 
Thanks,
Deepika. 
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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            top1.zip ‏3159 KB

嗨，您是否在设计中实例化IBUFDS，因为您已将其称为差分时钟？您是否在合成中禁用了“添加IO缓冲区”选项？此外，如果您在设计中实例化ibuf / ibufds，那么您应该使用输出端口
用于驱动负载的缓冲区。
你这样做吗？谢谢，迪丽卡。
谢谢，迪皮卡.----------------------------------------------
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以下为原文

Hi,

Did you instantiate IBUFDS in the design as you have mentioned it as differential clock?

did you disable the "add IO buffers" option in synthesis?

Also if you are instantiating ibuf/ibufds in the design then you should use the output port of the buffer to drive the loads. Are you doing this?

Thanks,
Deepika.Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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感谢您的回复，Deepika！
请允许我在我的设计中澄清更多：
引脚INCLK（差分时钟） - > IBUFDS  - >输出“sys_clk_buf”--- | -----------> PLL 
| -----------> DDR Bank1 
| -----------> DDR Bank3
//////////////////////////////////////////////////
//////////////////////////////////////////////////
////////
模块顶部
（
INCLK_P，
INCLK_N，
.........
）;
wire sys_clk_buf; IBUFGDS＃（。DIFF_TERM（“TRUE”））u_ibufg_sys_clk（.I（INCLK_P）,. IB（INCLK_N）,. O（sys_clk_buf））; syspll isyspll（//端口中的时钟.CLK_IN1（sys_clk_buf），
........................
）;
phy16_B1_B3 u_phy16_B1_B3 //适用于Bank1＆amp ;;的MIG DDR2
Bank3（.c1_sys_clk（sys_clk_buf），
..................................................
................. 
.c3_sys_clk（sys_clk_buf），
..................................................
.................
）;
endmodule
//////////////////////////////////////////////////
//////////////////////////////////////////////////
////////
但我仍然收到其他错误消息。
“NgdBuild：455  - 逻辑网'sys_clk_buf'有多个驱动程序：块u_ibufg_sys_clk上的引脚O，类型为IBUFGDS，块PAD上的块为sys_clk_buf，类型为PAD”
“NgdBuild：462  - 输入焊盘网'sys_clk_buf'驱动多个缓冲区：块上的引脚I isyspll / clkin1_buf类型为IBUFG，引脚I位于块u_phy16_B1_B3 / memc3_infrastructure_inst / se_input_clk.u_ibufg_sys_clk，类型为IBUFG，引脚I位于块u_phy16_B1_B3 / memc1_infrastructure_inst / se_input_clk
类型为IBUFG的.u_ibufg_sys_clk“
我上面有错吗？
谢谢，



以下为原文

Thanks for your reply, Deepika!
 
Pls give me to clarify more in my design:
pin INCLK (diffrential clock) --> IBUFDS --> output "sys_clk_buf" ---|-----------> PLL
                                                                                                                        |-----------> DDR Bank1
                                                                                                                        |-----------> DDR Bank3
////////////////////////////////////////////////////////////////////////////////////////////////////////////
module top
(
INCLK_P,
INCLK_N,
.........
);
wire         sys_clk_buf;
IBUFGDS #(.DIFF_TERM ("TRUE"))  u_ibufg_sys_clk ( .I(INCLK_P), .IB(INCLK_N), .O(sys_clk_buf));
syspll isyspll
 (// Clock in ports
  .CLK_IN1(sys_clk_buf),
........................
);
 
phy16_B1_B3 u_phy16_B1_B3   //MIG DDR2 for Bank1 & Bank3
    (
     .c1_sys_clk           (sys_clk_buf),
...................................................................
     .c3_sys_clk           (sys_clk_buf),
...................................................................
);
endmodule
////////////////////////////////////////////////////////////////////////////////////////////////////////////
But I still get other error messages.
"NgdBuild:455 - logical net 'sys_clk_buf' has multiple driver(s):
  pin O on block u_ibufg_sys_clk with type IBUFGDS,
  pin PAD on block sys_clk_buf with type PAD"
"NgdBuild:462 - input pad net 'sys_clk_buf' drives multiple buffers:
  pin I on block isyspll/clkin1_buf with type IBUFG,
  pin I on block u_phy16_B1_B3/memc3_infrastructure_inst/se_input_clk.u_ibufg_sys_clk with type IBUFG,
  pin I on block u_phy16_B1_B3/memc1_infrastructure_inst/se_input_clk.u_ibufg_sys_clk with type IBUFG"
 
Do I have some mistake in above?
 
Thanks,

嗨，
对我来说，看起来有IBUF / IBUFGDS的级联导致了这个问题。
应该只有一个输入缓冲区。
modulessyspll，phy16_B1_B3已经在其中包含输入缓冲区IBUFG，因此当您在TOP级别实例化IBUFGDS时会出现错误。
这些模块是否作为网表（NGC / EDIF）添加到项目中？
如果是，在生成网表（NGC / EDIF）时，您是否在合成期间禁用了-add io buffers选项？
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
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如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
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以下为原文

Hi,
 
For me it looks like there is cascading of IBUF/IBUFGDS which is causing the problem. There should be only one input buffer.
 
The modules syspll,phy16_B1_B3 already have input buffers IBUFG inside them and hence when you are instantiating IBUFGDS at TOP level there is an error.
 
Are these modules added as netlists(NGC/EDIF) in the project? If yes, while generating the netlist(NGC/EDIF) did you disable the -add io buffers option during synthesis?
 
Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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谢谢你的快速回复，
“这些模块是否在项目中添加为网表（NGC / EDIF）？如果是，在生成网表（NGC / EDIF）时，您是否在合成期间禁用了-add io缓冲区选项？”
---->问题是如何禁用它们？
在wizare中，我看不出这个选项在哪里。
当我在“Xilinx特定选项”标签中禁用时，结果是相同的。
谢谢



以下为原文

Thanks for your fast reply,
"Are these modules added as netlists(NGC/EDIF) in the project? If yes, while generating the netlist(NGC/EDIF) did you disable the -add io buffers option during synthesis?"
----> the question is how can I disable them?
In the wizare, I can not see where this option is. When I disabled in the "Xilinx Specific Option" tag, the result is the same.
 
Thanks

嗨，
是否可以共享测试用例以便我们检查？
你在设计中有NGC / EDIF吗？
如果是，则需要通过禁用“添加IO缓冲区”来重新生成NGC，即合成设置。
这需要为子模块网表生成（不是顶层模块）完成。
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
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以下为原文

Hi,
 
Is it possible to share the test case so that we can check this?
 
Do you have NGC/EDIF in the design? If yes, then you need to re-generate the NGC by disabling the "Add IO buffers" is synthesis settings. This needs to be done for the submodules netlist generation (not the top module).
 
 
Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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嗨Deepika，
请检查附件。
这个文件是原创的我创建的项目，它没有包含NGC的子模块。
然后我尝试为子模块生成NGC（如上所述禁用Add I / O Buffers）并包含到项目中，但仍然收到错误消息。
我对此很少有经验。
谢谢你的帮助！
top.zip 2425 KB



以下为原文

Hi Deepika,
Pls check attach file. This file is original I created the project, it did not include NGC for sub-modules.
Then I tried to generate NGC for the sub-modules (with disable Add I/O Buffers as you said) and include into the project, but still got the error messages.
I have a very little experience in this. Thanks for your help!
 
            top.zip ‏2425 KB

嗨，
我不确定你的设计要求。
但是从帖子中我了解到你需要一个如下界面：
clk_p-- | -------- -------- IBUFGDS | --MIG
clk_n-- |
|  - 时钟精灵
如前所述，错误是由于级联ibuf。
MIG和时钟向导内部有IBUF，并提出问题。
您可以通过以下选项在时钟向导中禁用此输入缓冲区：
如上所示，您需要通过为时钟输入选择“No buffer”来重新设置cloking向导核心。
对于MIG，我不认为可以选择禁用这样的缓冲区。
在这种情况下，您需要编辑MIG生成的infrastructure.v文件并注释IBUFG / IBUFGDS并保存。
我做了以上修改，现在设计通过翻译阶段。
请检查附件项目。
还要重新检查它是否符合您的设计需求。
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）
top1.zip 3159 KB



以下为原文

Hi,
 
I am not sure of your design requirements. But from the posts I understood that you need an interface as below:
 
clk_p--|--------IBUFGDS--------|--MIG
clk_n--|                                       |--clocking wizard
 
As already mentioned the error is due to cascading ibuf. The MIG and clocking wizard internally have IBUF in them and cauing the issue. You can disable this input buffer in clocking wizard by the below option:
 

 
You need to regernate the cloking wizard core by selecting "No buffer" for clock input as shown above.
 
For MIG I dont think there is option to disable buffers like this. In this case you need to edit the MIG generated infrastructure.v file and comment the IBUFG/IBUFGDS and save it. 
 
I made the above changes, now the design passes translate phase. Please check the attached project. Also recheck if it meets your design needs.
 
Thanks,
Deepika. 
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)            top1.zip ‏3159 KB

再次感谢您的帮助，Deepika！



以下为原文

Again, Thanks for your good helps, Deepika!