请问我可以在流程中调用组件吗？

>我可以在流程中调用组件
不，这是不允许的。
为什么你认为你想要这样做？
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> can i call component inside the process
 
No, this is not allowed.   Why do you think that you would want to do this?
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

你不用硬件“召唤”任何东西。
您似乎缺少对硬件描述语言以及数字设计的基本理解。
你究竟想做什么？
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

You do not "call" anything in hardware.
 
You seem to be missing a fundamental understanding of hardware description languages and, by extension, digital design.
 
What exactly is it that you are trying to do?
 
----------
"That which we must learn to do, we learn by doing." - Aristotle

对不起，我明白，不要在硬件中调用任何东西，但我希望makecomponent内部条件，如if或when或任何其他条件，我可以这样做？
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-----------------------------如果你在后面刺伤，知道你在前台--------
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以下为原文

sorry
i understand that not call anything in hardware but i wish make
component inside condition such as if or when or any other condition
can i do this ?-------------------------------------------------------------------------------
If you stabbed in the back, know you are in the foreground
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sarmad88写道：对不起我明白，不要在硬件中调用任何东西，但我希望makecomponent内部条件，如if或when或任何其他条件，我可以这样做？
霍华德是对的。
你在想软件。
这是硬件设计。
组件在构建时实例化，或者不是。
也许如果你描述一下你想要实现的目标，我们可以引导你走向正确的方向（也许是为了营销事业）？
----------------------------是的，我这样做是为了谋生。



以下为原文

sarmad88 wrote:
sorry
i understand that not call anything in hardware but i wish make
component inside condition such as if or when or any other condition
can i do this ?

Howard's correct. You're thinking software. This is hardware design.
 
Either the component is instantiated at build time or it's not.
 
Perhaps if you describe what you're trying to accomplish we can steer you in the correct direction (perhaps, to a career in marketing)?
----------------------------Yes, I do this for a living.

谢谢你，我明白了
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-----------------------------如果你在后面刺伤，知道你在前台--------
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以下为原文

thank you vary much
i understand that
-------------------------------------------------------------------------------
If you stabbed in the back, know you are in the foreground
--------------------------------------------------------------------------------

>但我希望将组件置于条件内，例如if或when或其他条件
组件是一个硬件模块，它可以完成“填充”（东西=你设计它的目的），并且它总能完成它设计的“东西”。
如果您希望设计使用模块执行不同的操作，则需要更改模块代码（可能添加一个或多个端口）或更改模块输入用于实现功能的方式
例如，如果您的组件是一个通用的8位计数器，在您的设计中使用的计数从0到999，它将看起来像这样。
计数器模块（Verilog不是VHDL，因为它更容易）：
模块my_counter（clk，en，reset，count）
输入clk;
输入en;
输入复位;
输出reg [7：0]计数;
永远@（posedge clk）
开始 
如果（重置） 
计数
这将在你的设计中实例化如下：
最佳 （.....）
..
..
my_counter U0（.clk（clk）,. en（en）,. redset（reset）,. count（count））;
assign en =（count
但是现在你想要添加一个函数，这样只有在按下一个按钮时才能计算，你可以这样做，而不需要改变模块代码。
最佳 （.....）
..
..
my_counter U0（.clk（clk）,. en（en）,. redset（reset）,. count（count））;
assign en =（count
另一种方法是将按钮添加到模块作为附加输入，并通过按钮输入更改代码以限定计数启用，如下所示：
模块my_counter（clk，en，pushbutton，reset，count）
输入clk;
输入en;
输入按钮;
输入复位;
输出reg [7：0]计数;
永远@（posedge clk）
开始 
如果（重置） 
计数
注意：不要将时钟输入连接到模块。
这是一个非常糟糕的设计实践。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> but i wish make component inside condition such as if or when or any other condition

A component is a hardware module that does "stuff"  (stuff = what you designed it to do) and it always does the "stuff" that it was designed to do.   If you want the design to use the module to do something different then you need to either change the module code (potentially adding one or more ports) or change the way that the module inputs are used to be able to implement the function
 
For instance if you had a component that was a generic 8 bit counter that was used in your design to count from 0 to 999 it would look something like this.
 
The counter module (Verilog not VHDL as it is easier):
module  my_counter (clk, en, reset, count)input clk;input en;input reset;output reg [7:0] count;always @ (posedge clk)begin   if (reset)      count <= 8'b0;   else if (en)      count <= count + 1'b1;endendmoduleAnd this would be instantiated in your design like this:
 
top (.....)....my_counter U0 (.clk(clk), .en(en), .reset(reset), .count(count));assign en = (count < 999) ? 1'b1 : 1'b0;But now you want to add a function so that it only counts if a push button is asserted you could do it like this without changing the module code.
 
top (.....)....my_counter U0 (.clk(clk), .en(en), .reset(reset), .count(count));assign en = (count < 999 && pushbutton) ? 1'b1 : 1'b0; 
The alternative is to add the push button to the module as an additional input and to change the code to qualify the count enable with the push button input and that would look like this:
 
module  my_counter (clk, en, pushbutton, reset, count)input clk;input en;input pushbutton;input reset;output reg [7:0] count;always @ (posedge clk)begin   if (reset)      count <= 8'b0;   else if (en && pushbutton)      count <= count + 1'b1;endendmodule 
Note: Do not gate the clock inputs to modules.  This is a very bad design practice.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

抱歉
我使用VHDL notVerilog
请在VHDL代码中显示相同的示例
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-----------------------------如果你在后面刺伤，知道你在前台--------
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以下为原文

sorry 
i use VHDL not Verilog 
please can you show the same example in VHDL code 
-------------------------------------------------------------------------------
If you stabbed in the back, know you are in the foreground
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我发布的Verilog代码只是一个例子来解释这个概念，以防它不清楚。
您应该能够自己找出VHDL版本，因为差异很小，最好的学习方法就是完成工作。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

The Verilog code that I posted was just an example to explain the concept in case it wasn't clear.   You should be able to figure out the VHDL version on your own as the difference are minor and the best way to learn is by doing the work.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

sarmad88写道：
抱歉
我使用VHDL notVerilog
请在VHDL代码中显示相同的示例
Verilog和VHDL足以让您理解Ed的概念。
----------------------------是的，我这样做是为了谋生。



以下为原文

sarmad88 wrote:
sorry 
i use VHDL not Verilog 
please can you show the same example in VHDL code 

Verilog and VHDL are similar enough for you to understand Ed's concept.
----------------------------Yes, I do this for a living.

我不太清楚我明白你想做什么，但听起来你想要使用VHDL if..generate语句？
请阅读Peter Ashenden的书“VHDL设计师指南”封面。
无论如何，一个例子是： 
如果我> 0生成 
U1：FOOBAR端口映射 
（A（I），B（I），C（I-1），S（I），C（I））; 
结束生成;
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-------------------------------我喜欢这些书：Free Range VHDL（免费），http：//www.freerangefactory
.org / site / pmwiki.php / Main / BooksVHDL for Logic Synthesis，Andrew RushtonFPGA Prototyping by VHDL examples，Pong P Chu



以下为原文

Not quite sure I understand what you want to do but it sounds like you want to use the VHDL if..generate statement? Please read Peter Ashenden's book "The Designer's Guide to VHDL" cover to cover. Anyway an example would be:
 
    if I>0 generate      U1: FOOBAR port map         (A(I),B(I),C(I-1),S(I),C(I));    end generate;---------------------------------------------------------------------------------
I like these books:
Free Range VHDL (free), http://www.freerangefactory.org/site/pmwiki.php/Main/Books
VHDL for Logic Synthesis, Andrew Rushton
FPGA Prototyping by VHDL Examples, Pong P Chu

忘了补充一点，这在流程中不起作用。
而我犯了一个错误，生成声明需要有一个标签......
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-------------------------------我喜欢这些书：Free Range VHDL（免费），http：//www.freerangefactory
.org / site / pmwiki.php / Main / BooksVHDL for Logic Synthesis，Andrew RushtonFPGA Prototyping by VHDL examples，Pong P Chu



以下为原文

Forgot to add that this won't work inside a process. And I made a mistake, generate statement are required to have a label...---------------------------------------------------------------------------------
I like these books:
Free Range VHDL (free), http://www.freerangefactory.org/site/pmwiki.php/Main/Books
VHDL for Logic Synthesis, Andrew Rushton
FPGA Prototyping by VHDL Examples, Pong P Chu

rlewis65写道：忘了添加，这将无法在进程内工作。
而我犯了一个错误，生成声明需要有一个标签......
当然，生成是一个编译时构造。
我认为原来的海报是一个软件家伙谁喝“高清晰度就像编程！”
库尔急救。
----------------------------是的，我这样做是为了谋生。



以下为原文

rlewis65 wrote:
Forgot to add that this won't work inside a process. And I made a mistake, generate statement are required to have a label...

Generate, of course, is a compile-time construct.
I think the original poster is a software guy who drank the "HDL is just like programming!" Kool-Aid.
----------------------------Yes, I do this for a living.

我第一次学习HDL（在这种情况下是VHDL）时犯了同样的错误。
我已经专业编程了25年以上，当我购买我的第一块FPGA板时，我想：“这很简单，我只需编写我的”代码“，”编译“它，上传”可执行文件“并点击”
运行“按钮...男孩，我错了。想想我花了整整一个星期的时间来绕过一个闪烁的LED指示灯。我现在已经到了能够构建相当复杂和大型设计的地步
拉出我的头发（无论如何还剩下什么），但这并不容易。
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-------------------------------我喜欢这些书：Free Range VHDL（免费），http：//www.freerangefactory
.org / site / pmwiki.php / Main / BooksVHDL for Logic Synthesis，Andrew RushtonFPGA Prototyping by VHDL examples，Pong P Chu



以下为原文

I made the same mistake when I first learned an HDL (VHDL in this case). I've been programming professionally for 25+ years and thought when I purchased my first FPGA board: "This will be easy, I'll just write my "code", "compile" it, upload the "executable" and hit the "run" button... Boy how I was wrong. Think it took me an entire week to wrap my head around how to blink a f'ing LED. I'm now to the point where I can build reasonably complex and large designs without pulling my hair out (what's left of it anyway)  but it wasn't easy. 
---------------------------------------------------------------------------------
I like these books:
Free Range VHDL (free), http://www.freerangefactory.org/site/pmwiki.php/Main/Books
VHDL for Logic Synthesis, Andrew Rushton
FPGA Prototyping by VHDL Examples, Pong P Chu

我们都错误地开始但是vhdl改变了我的想法180度每个工程师必须知道这种语言
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-------------------------------------------我厌倦了传统
人民 - 我想要的是与我爱的女孩一起自由生活 - 但这是不可能的，因为人民的传统比我强.------------------
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以下为原文

we all do mistake at starting
but the vhdl change my mind 180 degree
every engineer must know this language
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I am tired of the traditions of peoples                                                       --
All I want is to live freely with the girl which I love                                   --
But this is impossible because the traditions of the people stronger than me.
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每个工程师都必须懂这种语言
坦率地说，这是更大问题的一部分。
有了耐心和指导，任何人都可以学习任何语言的语法。
缺少的是对数字逻辑设计的基本掌握。
如果您无法想象硬件是否正在尝试设计，使用HDL进行捶打，希望找到可合成的解决方案，这是浪费每个人的时间。
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

every engineer must know this language
Quite frankly, this is part of the bigger problem.

 
Given patience and guidance, anyone can learn the syntax of any language. What is missing is a fundamental grasp of digital logic design.
 
If you can't conceive the HARDWARE of what you are trying to design, thrashing around with an HDL, hoping to fall onto a synthesisable solution, is a waste of everybody's time. 
----------
"That which we must learn to do, we learn by doing." - Aristotle