S6 IODELAY2校准错误

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以下为原文

You are describing the problem as if we are in the same room with you and as if we can read and understand your code.
 
Unfortunately, we are not in the same room with you and we have not seen your code and we do not understand what your design is trying to do.  Please be more specific when you are mention "the state machine" and "the busy" and "few short pulses" and "everything works".
 
Trying to reconstruct your design and your code from the clues you have given us is very time-consuming and error-prone, so please tell us:
 

• what are you trying to do
  
• how are you doing it
  
• what tests have you run
  
• what works
  
• what doesn't work
  

 
It will be much easier to help you with a bit more information.
 
-- Bob Elkind
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>频率约为66MHz的信号.....向主从设备发出校准命令
对于IODELAY2校准功能，66 MHz（可能是66 Mbps）太慢（参见Spartan-6数据手册中的表39）。
没有必要将这些高速捕获技术与运行缓慢的信号一起使用。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

>  signal with frequency around 66MHz.....issues a calibrate command to both master and slave iodelays
 
66 MHz (and likely 66 Mbps) is too slow for the IODELAY2 calibration function (see table 39 in the Spartan-6 data sheet).
 
There is no need to use these high speed capture techniques with signals that run this slow.
 
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

对于IODELAY2校准功能，> 66 MHz（可能是66 Mbps）太慢
谢谢mcgett，这也是我的假设，现在确认了:-)
@Bob，
我只是想确认问题是由于低频而不是vhdl。
这就是为什么我没那么具体......
这是我有的：
我有一个发送到目标设备的时钟和数据输出线，我从设备返回数据。
时钟必须是可编程的，因此用户可以选择低至几kHz且尽可能高的时钟。
高达20-30Mhz我不需要去除信号。
高于188MHz我可能会使用相位检测器和偏移校正逻辑。
但问题是我之间做了什么？
请注意，延迟是未知的，我确信在没有偏移校正逻辑的情况下，无法捕获100MHz范围内的信号。
顺便说一句，从一开始我就预料到IODelay2自动校准将不起作用。
所以我计划“B”，我希望相位检测器逻辑可以在任何频率下工作，只要我能提供以下内容：
1）主和从IODelays采样点之间的固定延迟，其不超过数据眼的1/2并且不小于某个临界最小值。
2）为了处理VALID和INCDEC命令，我必须能够在我的时钟的整个时钟周期内移动两个采样点（无论频率如何）。
现在，没有校准我无法测量数据眼。
但我认为这不是一个大问题，因为我可以指定它必须至少为2nS。
如果真正的窗口不是那么开放它无论如何都不会起作用。
真正的问题在于第二个要求。
假设我使用10ns时钟周期，但由于延迟线的限制，我不能有超过5.3nS的延迟。
然而，如果眼睛碰巧在时钟的前1/4  - 一切都很好。
我可以检查它是否正常。
现在让我们说眼睛不在前1/4所以我应该增加延迟。
但相反，我可以将我的IO时钟相移90度...如果这不起作用，我可以尝试180然后270度....所以有了可变相移功能，我可以增加延迟范围，或者至少
但愿如此 ;-）
你认为这可行吗？
谢谢，
米罗



以下为原文

>66 MHz (and likely 66 Mbps) is too slow for the IODELAY2 calibration function
 
Thank you mcgett, this was my assumption too and now it is confirmed :-) 
 
@Bob,
I just wanted to confirm that the problem is due to the low frequency not the vhdl.  That's why I was not so specific...
 
Here is what I have:
I have a clock and data-out line sent to a target device and I have data-in line back from the device. The clock must be programable so the user can select as low as few kHz and as high as it can get. Up to 20-30Mhz I don't need to deskew the signal. Above 188MHz I can use the phase detector and deskew logic probably.
 
But the question is what I do in between?
 
Note that the delay is unknown and I am quite sure there is no way to capture a signal in the 100MHz range without deskew logic.
 
Btw from the very beginning I have expected that the IODelay2 auto calibration won't work. So I have plan "B", and I hope that the Phase Detector logic will work with any frequency as long as I can provide the following:
 
1) fixed delay between the master and slave IODelays sampling points, which is not more than the 1/2 from the data eye and not less than some critical minimum.
2) In order to process the VALID and INCDEC commands I must be able to move both sampling point across the entire clock period of my clock (whatever the frequency is).
 
Now, without calibration I cannot measure the data eye. But I think this is not that big problem because I can specify that it must be at least 2nS. If the real window is not that much open it will not work anyway. 
The real problem is with the second requirement. Let say I use 10ns clock period but due to the limitation of the delay lines I cannot have delays more than 5.3nS. However if the eye happens to be in the first 1/4 of the clock - everything is OK. And I can check that it is OK. Now let's say the eye is not in the first 1/4 so I am supposed to increase the delays. 
But instead I can phase shift my IO clock with 90 degrees... If this doesn't work I can try 180 and then 270 deg.... So with the variable phase shift capabilities I can increase the delay range, or at least I hope so ;-)
 
Do you think this can work?
 
Thanks,
Miro

在这里，我们走了...这是我的头脑，没有完全考虑，所以它可能或多或少脑损伤。
在一个PLL中为结构逻辑生成333MHz时钟，接近Spartan-6器件的频率限制。
将333MHz时钟分频为时基TIMEBASE1，可用于生成所需的时钟频率。
TIMEBASE1将由第二个PLL使用。
TIMEBASE1必须具有50％的占空比。
TIMEBASE1频率必须在2：1的频率范围内。
第二个PLL将使用此TIMEBASE1生成500MHz至1GHz范围内的IO时钟，以及62.5MHz至125MHz范围内的（1/8）结构时钟。
这两个时钟都将锁定到TIMEBASE1。
IO时钟频率是所需串行数据速率的偶数整数倍。
使用OSERDES2块和结构逻辑，生成外部设备的SERIAL_CLOCK。
SERIAL_CLOCK的频率范围为DC至500MHz（I / O时钟频率的上限除以2）。
输入串行数据速率与SELER_CLOCK频率相同。
IDELAY2块将串行数据与IO时钟对齐，ISERDES2块以1：8的方式对数据进行反序列化。
完全取决于结构逻辑，对反序列化数据进行字构设。
对于低频操作，串行数据将被严格过采样并需要进行抽取。
由于结构逻辑和ISERDES2块以及串行输入数据和SERIAL_CLOCK都被锁定到相同的TIMEBASE1时基，所以一切正常。
用于生成TIMEBASE1，用于生成SERIAL_CLOCK以及用于字段成帧（和抽取）输入数据的分频器可以存储在查找表中以便于设计。
总之，这种方法使用所需串行数据频率的最高可用偶数整数倍 - 在单个倍频程范围内，以保持第二个PLL满意 - 运行设计。
这使IOCLOCK在可变延迟模式下保持在IDELAY2块的操作范围内。
我没有想到这一点，所以可能需要一些审查和一些调整。
欢迎提出意见和修改。
笔记：
生成的时基不比第一个PLL的源时钟更好（准确，稳定，精确）。
对于MEMEBASE1的单倍频程（2：1）范围可能是不必要的限制，但它应该是可行的。
它极大地简化了逻辑，使IO时钟和SERIAL_CLOCK之间的频率比保持均匀。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

Here we go...  This is off the top of my head, not completely thought out, so it may be more or less brain-damaged.
 
Generate a 333MHz clock for fabric logic, near the frequency limit for Spartan-6 devices, in one PLL.
 
Divide this 333MHz clock to a timebase TIMEBASE1 which can be used to generate the clock frequency you desire.
TIMEBASE1 will be used by a second PLL.
TIMEBASE1 must have 50% duty cycle.
TIMEBASE1 frequency must fall within a 2:1 frequency range.
 
The second PLL will use this TIMEBASE1 to generate an IO clock in the range of 500MHz to 1GHz, and a (1/8) fabric clock in the range of 62.5MHz to 125MHz.  Both of these clocks will be locked to TIMEBASE1.  The IO clock frequency is an even integer multiple of the desired serial data rate.
 
Using an OSERDES2 block and fabric logic, the SERIAL_CLOCK for the external device is generated.  The frequency range of SERIAL_CLOCK is DC to 500MHz (upper limit of I/O clock frequency divided by 2).
 
Input serial data rate is the same as SERIAL_CLOCK  frequency.  IDELAY2 blocks align the serial data to the IO clock, and the ISERDES2 blocks deserialise the data by 1:8.  It is entirely up to the fabric logic to word-frame the deserialised data.
 
For low-frequency operation, the serial data will be grossly over-sampled and will need to be decimated.  Because the fabric logic and the ISERDES2 blocks and serial input data and SERIAL_CLOCK are all locked to the same TIMEBASE1 timebase, everything works.
 
The dividers for generating TIMEBASE1, for generating SERIAL_CLOCK, and for word framing (and decimating) input data can be stored in a lookup table for design simplicity.
 
This approach, in sum, uses a highest usable even integer multiple of the desired serial data frequency -- within a single octave range, to keep the second PLL happy -- to run the design.  This keeps the IOCLOCK within the operating range for the IDELAY2 blocks in variable delay mode.
 
I haven't thought this through, so it may need some review and some tweaking.  Comments and revisions are welcome.
 
NOTES:

• The generated timebases are no better (accurate, stable, precise) than the source clock for the first PLL.
  
• The single-octave (2:1) range for TIMEBASE1 may be unnecessarily restrictive, but it should be workable.
  
• It greatly simplifies the logic to keep the frequency ratio between the IO clock and SERIAL_CLOCK an even integer.
  

 -- Bob Elkind
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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谢谢Bob，
恐怕我没有告诉你整个故事......事实上界面是jtag / swd，我正在做的是一个调试器。
我们在标记上有很多年，当前版本的工作方式与您的建议非常相似。
在启动时，我们将目标置于旁路模式，然后我们开始测量序列。
您可以想象我们无法控制电缆长度，缓冲区等，因此延迟可能会有很大差异。
无论如何，我们发送一个已知的模式，我们尝试各种捕获偏移，直到我们得到正确的接收。
这适用于许多目标。
但不幸的是，几乎没有例外。
某些目标不是完全同步的，或者它们具有不同的内部路径。
当我们将它们置于旁路模式或选择标准TAP寄存器时，它们不会显示任何延迟。
但是当访问一些内部寄存器时，我们得到了延迟。
我想这是由于它们的CPU时钟域和jtag的TCK域之间的同步。
通常这种延迟与时钟周期相比较小，但由于我们处理的信号完整性较差，因此我们的眼窗非常有限。
所以我们校准到一个延迟，它可以在运行中改变。
问题是我们不知道期望什么数据，所以我们无法捕捉错误。
这就是我查看相位检测器功能的原因。
我希望我可以用它来动态调整延迟而不需要知道数据。
当然，在开始时，我将使用特殊数据模式进行粗延迟测量。
所以问题是关于相位检测器逻辑 - 从文档中不清楚它是否适用于低速运行？
如果它不起作用，我将尝试类似你的方法Bob，但没有IODelays2s  - 它们不稳定（温度等）。
米罗



以下为原文

Thank you Bob,
 
I am afraid I haven't told you the whole story... In fact the interface is jtag/swd and what I am doing is a debugger. We are many years on the marked and the current version works with approach which is quite similar to what you suggest.
At startup we put the targets in bypass mode and then we start measurement sequence. As you can imagine we don't have control over the cable length, buffers etc, so the delay can vary a lot. Anyway, we send a known pattern and we try various capture offsets until we get a correct reception.
 
This works for many targets. But unfortunately there are few exceptions. Some targets are not quite synchronous or they have different internal paths. When we put them in a bypass mode or select the standard TAP registers they don't show any delay. But when accessing some internal registers we got a delay. I suppose this is due to the synchronization between their CPU clock domain and the jtag's TCK domain. Typically this delay is small compared with the clock period, but since we deal with poor signal integrities our eye window is quite limited.
So we calibrate to one delay and it can change on the fly. The problem is that we have no clue what data to expect so we can't catch the errors.
 
That's why I look at the Phase Detector feature. I hope I can use it to dynamically adjust the delays without knowing the data. Of course in the beginning I will have a coarse delay measurement using a special data pattern.
 
So the question is about the Phase Detector logic – it is not clear from the documentation will it work for low speed or not?
 
If it does not work I will try something like your approach Bob, but without IODelays2s - they are not stable (temperature etc).
 
Miro

所以问题是关于相位检测器逻辑 - 从文档中不清楚它是否适用于低速运行？
mcgett在帖子＃3中写的这个帖子是正确的。
表39中的F（mincal）DS162数据表规范是明确的。
IDELAY块的延迟范围是有限的，这对IOCLOCK周期施加了最大限制（即最小IOCLOCK频率要求）。
但没有IODelays2s  - 它们不稳定（温度等）。
你有什么选择？
输入缓冲器，输入寄存器和时钟缓冲器的延迟在过程，温度和电压方面也“不稳定”。
这就是IDELAY2模块旨在克服的问题。
IDELAY2块中P / T / V变化的对策是校准。
当然，这仅在高比特率时才有意义。
听起来你很了解潜在的问题。
我期待着您对预期设计方法的描述。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

So the question is about the Phase Detector logic – it is not clear from the documentation will it work for low speed or not?
 
What mcgett wrote in post #3 in this thread is correct.  The DS162 datasheet specification for F(mincal) in Table 39 is unambiguous.  The delay range of IDELAY block is limited, and this imposes a maximum limit on the IOCLOCK period (i.e. a minimum IOCLOCK frequency requirement).
 
but without IODelays2s - they are not stable (temperature etc).
 
What is your alternative?  The delays of the input buffers, input registers, and clock buffers are also 'not stable' over process, temperature, and voltage.  That's the problem which the IDELAY2 blocks were designed to overcome.  The countermeasure for P/T/V variations in IDELAY2 blocks is calibration.  This only matters at high bit rates, of course.
 
It sounds like you understand the underlying issues quite well.  I'm looking forward to your description of your intended design approach.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

>你有什么选择？
我的想法是：
1）我将从属IODelay设置为零延迟，主设备延迟1 / 2X，其中“X”是我对预期眼宽的猜测。
2）我将使用标准的相位检测器逻辑，它被告知我是否存在VALID边沿以及是否必须更改延迟（INCDEC）。
3）我将遵循命令，但我也会跟踪所要求的增量＆amp;
减少步骤。
如果眼睛接近我的时钟周期的开始，我将锁定它。
否则，我认为相位检测器将要求越来越多的延迟。
但是当我达到最大值时，我会将延迟返回到初始值，然后我将相移IO时钟。
然后我将重新开始搜索。
总之：我将使用时钟相移作为粗略延迟，然后使用IODelay2进行微调。
关于“X”猜测...在启动时我会强制使用许多值并且将获得X的范围，所以在某种程度上这不会是一个疯狂的猜测，而是类似于一个测量。



以下为原文

>What is your alternative?
 
My idea is:
 
1)  I will set the slave IODelay to zero delay and the master to delay 1/2X, where "X" is my guess for the expected eye width.
2) I will use the standard Phase Detector logic, which is suppoused to tell me if the there is VALID edge and if I have to change the delay (INCDEC).
3) I will follow the commands but I will also keep track of the requested increment & decrement steps.
if the eye is close to the beginning of my clock period eventualy I will lock it. 
Otherwise I suppouse the phase detector will request more and more inrease in the delays. However when I reach the maximum I will return the delays to initial values and I will phase shift the IO clock. Then I will restart the search.
 
In sum:  I will use clock phase shifting as a coarse delay and then IODelay2s for fine tunning.
 
About the "X" guess... on startup I willl brute force many values and will get the range for X, so in a way this will not be a wild guess but something like a measuremnt. 
 

IDELAY2模块仅在需要提供IOCLOCK和IDELAY2校准的模式下可变，IOCLOCK频率范围以F（mincal）为界（DS162表39）。
这在IOCLOCK频率上设置了188MHz的下限。
使用DCM（而不是PLL）可以使用DCM的动态相移功能。
这在IOCLOCK频率上设置了375MHz的上限。
通过将DCM输出馈送到PLL进行固定倍频，可以将串行比特率范围和IOCLOCK频率范围扩展到375MHz以上。
你能解释一下如何使用超过IOCLOCK周期的粗调和细调偏差调整范围吗？
换句话说，在1个IOCLOCK周期的IDELAY2动态延迟调整范围在什么情况下是不够的？
- 鲍勃埃尔金德
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以下为原文

The IDELAY2 blocks are variable only in modes which require providing an IOCLOCK and IDELAY2 calibration, with an IOCLOCK frequency range bounded by F(mincal) (DS162 Table 39).  This places a 188MHz lower bound on IOCLOCK frequency.
 
Use of the the DCM (rather than PLL) allows the use of the DCM's dynamic phase shift capabilities.  This places a 375MHz upper bound on IOCLOCK frequency.
 
You can extend the serial bit rate range and IOCLOCK frequency range beyond 375MHz by feeding the DCM output to a PLL for fixed frequency multiplication.
 
Can you explain how you would use coarse and fine de-skew adjustment range which exceeds the IOCLOCK period?  In other words, in what circumstances would the IDELAY2 dynamic delay adjust range of 1 IOCLOCK period be insufficient?
 
-- Bob Elkind
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> IDELAY2块仅在需要提供IOCLOCK和IDELAY2校准的模式下可变
你确定？
在我理解规格的方式中，在IODELAY2的正常操作期间根本不需要时钟。
它有自己的环形振荡器驱动计数器......
IOCLOCK仅在校准期间用作（作为参考），但我不打算使用校准。
由于决定何时在校准模式和正常模式之间切换是从结构中的状态机获取的，因此我认为没有问题可以防止它进入校准模式。
>你能解释一下如何使用超过IOCLOCK周期的粗略和精细的偏斜调整范围吗？
假设我使用象限相移，因此我将有4个采样范围，在每个范围内，我也有256个可能的延迟。
总共1k个可能的样本点。
那么，根据频率，一些点可能重叠但是没关系。
上电后我将把jtag链置于旁路模式。
然后，我将使用已知数据模式对每个采样点进行测试。
通过分析糟糕和良好的结果，软件将获得眼睛的图像。
然后我将选择奴隶和主IODELAY的最佳象限和默认值。
该测试实际上将取代内置校准。
从这一点开始，我将启用相位检测器逻辑。
如果偏斜变化或温度变化，我希望我能从这个逻辑得到正确的INCDEC命令，我将相应地改变延迟...



以下为原文

>The IDELAY2 blocks are variable only in modes which require providing an IOCLOCK and IDELAY2 calibration

Are you sure? 
In the way I understand the specs no clock is required at all during the normal operation of IODELAY2. It has its own ring oscillator which drives a counter...
The IOCLOCK is used (as reference) only during calibration, but I am not going to use the calibration. Since the decision when to switch between calibration mode and normal mode is taken from a state machine in the fabric I see no problem to prevent it from going into calibration mode.
 
 


>Can you explain how you would use coarse and fine de-skew adjustment range which exceeds the IOCLOCK period?
 
Let's say I use quadrant phase shift so I will have 4 sampling ranges and in each range I also have 256 possible delays. In total 1k possible sample points.  Well, depending on the frequency some of the points may overlap but that is OK.
 
Now after power up I will place the jtag chain in bypass mode. Then I will do a test with known data pattern for each of these sampling points. By analyzing the bad and good results the software will get the picture of the eye.
Then I will select the best quadrant and the default values for the slave and master IODELAYs.  This test will actually replace the built-in calibration.
 
From this point I will enable the Phase Detector logic. If the skew change or the temperature change I hope I will get proper INCDEC command from this logic and I will change the delays accordingly...