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我希望更频繁地从FPGA启动GPS接收器。 十六进制串需要从FPGA发送到具有微控制器的GPS接收器,通过串行通信为 A0 A1 00 0F 01 01 07 D8 0B 0E 08 2E 03 09 C4 30 70 00 64 16 0D 0A 我希望在FPGA打开后将此十六进制字符串存储在块RAM中,以便FPGA可以在需要时检索此字符串 有没有办法用for循环来实现这个? 问候 费萨尔 以上来自于谷歌翻译 以下为原文 HI I wish to start a GPS receiver from FPGA more often . Hex string needs to be sent from FPGA to GPS receiver having microcontroller via serial comm is as A0 A1 00 0F 01 01 07 D8 0B 0E 08 2E 03 09 C4 30 70 00 64 16 0D 0A I wish to store this hex string in block RAM after FPGA is turned on , so that FPGA can retrieve this string whenever it is needed Is there any way to acheive this using for loop ? Regards Faisal |
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>有没有办法用for循环来实现这个目的?
费萨尔,你为什么还要继续使用循环? 循环用于软件,应该很少用于硬件。 您有22个数据字要发送,简单的计数器和案例状态就是您需要执行的操作。 永远@(posedge clk) 开始 如果(重置) 计数 如果你想继续使用循环,我建议你花时间学习简单的PicoBlaze微型钻头,并用PicoBlaze汇编代码编写。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 > Is there any way to acheive this using for loop ? Faisal, why do you continue to want to use loops? Loops are for software and should be rarely used in hardware. You have 22 data words to be sent and simple counter and case state is all that you need to do this. always @ (posedge clk)begin if (reset) count <= 0; else if (count < 22) count <= count+1;endalways @ (count)begin case (count) 0 : data <= 8'hA0; 1 : data <= 8'hA1; ...... 21: data <= 8'h0A; 22: data <= 8'h00; // end state default: data <= 8'h00; // default case just in case endcaseend If you want to continue to use loops I would suggest that you spend time learning the simple PicoBlaze microcontoller and write this in PicoBlaze assembly code. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.comView solution in original post |
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检查BRAM的语言模板。
模板中有一个'init'工具示例。 它没有很好的记录,但它足以让你在几个小时的“dorking”中找到它。 如果您使用CoreGen BRAM向导,则通过.coe文件存在init工具。 我认为该向导指向.coe文件格式的示例...如果没有,请在论坛中搜索该主题。 我确信之前已经讨论过了。 - 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 Check the Language Templates for BRAM. There is an 'init' facility example in the template. It's not well-documented, but it's enough to allow you to figure it out in a few hours of 'dorking around'. If you use the CoreGen BRAM wizard, there is an init facility by way of .coe file. I think the wizard points to examples of the .coe file format... if not, search the forums for the topic. I'm sure it's been discussed before. -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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>有没有办法用for循环来实现这个目的?
费萨尔,你为什么还要继续使用循环? 循环用于软件,应该很少用于硬件。 您有22个数据字要发送,简单的计数器和案例状态就是您需要执行的操作。 永远@(posedge clk) 开始 如果(重置) 计数 如果你想继续使用循环,我建议你花时间学习简单的PicoBlaze微型钻头,并用PicoBlaze汇编代码编写。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 以上来自于谷歌翻译 以下为原文 > Is there any way to acheive this using for loop ? Faisal, why do you continue to want to use loops? Loops are for software and should be rarely used in hardware. You have 22 data words to be sent and simple counter and case state is all that you need to do this. always @ (posedge clk)begin if (reset) count <= 0; else if (count < 22) count <= count+1;endalways @ (count)begin case (count) 0 : data <= 8'hA0; 1 : data <= 8'hA1; ...... 21: data <= 8'h0A; 22: data <= 8'h00; // end state default: data <= 8'h00; // default case just in case endcaseend If you want to continue to use loops I would suggest that you spend time learning the simple PicoBlaze microcontoller and write this in PicoBlaze assembly code. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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谢谢麦吉特
费萨尔,你为什么还要继续使用循环? 我打算避免这22行。 看来这是不可能的。 所以基于鲍勃的建议 我希望使用单端口只读内存,目的是我可以在coregen向导中存储此初始化字符串。 有一个 load init file选项,不知道如何创建这个.cue文件格式。 不确定 ??? 亲切的问候 费萨尔 以上来自于谷歌翻译 以下为原文 Thanks Mcgett Faisal, why do you continue to want to use loops? I was intending to avoid this 22 lines . It seems it is not possible. So Based on Bob's suggestion I wish to use single port read only memory aiming that I can store this initialization string at the coregen wizard. There is one load init file option , not sure how to create this .cue file format . Not sure ??? Kind Regards Faisal |
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费萨尔
如果您在.COE文件中遇到问题,如果需要,您可以随时准备好Ed的解决方案。 Ed的解决方案看起来很简单。 我不知道这是如何在遥远的国家(这是全球受众)翻译的,但在这个国家有一种说法: 皮肤猫的方法不止一种。 我的代码中没有任何生成循环。 但是我的代码在其他方面可能是循环的。 :) - 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 Faisal, If you have trouble with the .COE file, you always have Ed's solution at the ready, if needed. Ed's solution looks pretty simple. I don't know how this translates in far away countries (this is a global audience), but there is a saying in this country: There is more than one way to skin a cat.I don't have any generate loops in my code. But my code can be loopy in other ways. :) - Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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>我打算避免这22行。
那么你写了50多行论坛帖子,而不是编写22行代码? 即使使用循环,您仍然需要相同的数据。 这里显示了另一种选择: 永远@(posedge clk) 开始 如果(重置)开始 数据 HDL线的数量对最终结果并不重要。 然而,HDL描述的内容确实很重要。 我发布的第一个代码将生成5个寄存器,可能是30-40个LUT。 第二个代码几乎是所有寄存器,将消耗181个寄存器和10-15个LUT。 使用BlockRAM的替代方案将消耗5个寄存器,10-15个LUT和一个BlockRAM。 由于BlockRAMs以这种有限的方式限制使用,因此是不可取的。 转移到分布式LUT RAM将消耗大约5个寄存器,10-15个LUT和8个LUT RAM ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 以上来自于谷歌翻译 以下为原文 > I was intending to avoid this 22 lines . So instead of writing 22 lines of code, you wrote 50+ lines of forums posts? Even with a loop you would still need the same data. An alternative is shown here: always @ (posedge clk)begin if (reset) begin data <= 176'hA0A1000F010107D80B0E082E0309C430700064160D0A; count <= 0; end else if (count < 22) begin data <= {8'h00, data[175:8]}; count <= count + 1; endend assign data_out = data[7:0]; The amount of HDL lines is not important to the end result. What the HDL describes however does matter. The first code that I posted would genarate 5 registers and maybe 30-40 LUTs. The second code is nearly all registers and would consume 181 registers and 10-15 LUTs. The alternative with a BlockRAM would consume 5 registers, 10-15 LUTs and a BlockRAM. Since BlockRAMs are limited using one in this limited fashion would be undesirable. Moving to distributred LUT RAMs would consume about 5 registers, 10-15 LUTs and 8 LUT RAMs ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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谢谢mcgett
那么你写了50多行论坛帖子,而不是编写22行代码? 抱歉。 我同意。 哎呀! 我再次在论坛中添加线条:smileyindifferent: 干杯 费萨尔 以上来自于谷歌翻译 以下为原文 Thanks mcgett So instead of writing 22 lines of code, you wrote 50+ lines of forums posts? Sorry. I agree. Oops ! Again I am adding lines to the forum :smileyindifferent: Cheers Faisal |
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None
以上来自于谷歌翻译 以下为原文 Bob, If want to write some 200 bytes of data into the blockram using the init template,read & write width would be 8 bits. It means INIT_00 => x"0A"; right? but how we'll manage to connect readaddr port &wrddr port .how/to which signal we'll map this ports ? & also if we are writing initial data(hardcoding) into block ram what will be DI => DI, -- Input write data port, width defined by WRITE_WIDTH parameter be connected to ? with ref to this --BRAM_SDP_MACRO : In order to incorporate this function into the design, -- VHDL : the following instance declaration needs to be placed -- instance : in the architecture body of the design code. The -- declaration : (BRAM_SDP_MACRO_inst) and/or the port declarations -- code : after the "=>" assignment maybe changed to properly -- : reference and connect this function to the design. -- : All inputs and outputs must be connected. -- Library : In addition to adding the instance declaration, a use -- declaration : statement for the UNISIM.vcomponents library needs to be -- for : added before the entity declaration. This library -- Xilinx : contains the component declarations for all Xilinx -- primitives : primitives and points to the models that will be used -- : for simulation. -- Copy the following four statements and paste them before the -- Entity declaration, unless they already exist. Library UNISIM; use UNISIM.vcomponents.all; Library UNIMACRO; use UNIMACRO.vcomponents.all; -- <-----Cut code below this line and paste into the architecture body----> -- BRAM_SDP_MACRO: Simple Dual Port RAM -- Virtex-6 -- Xilinx HDL Language Template, version 13.4 -- Note - This Unimacro model assumes the port directions to be "downto". -- Simulation of this model with "to" in the port directions could lead to erroneous results. ----------------------------------------------------------------------- -- READ_WIDTH | BRAM_SIZE | READ Depth | RDADDR Width | -- -- WRITE_WIDTH | | WRITE Depth | WRADDR Width | WE Width -- -- ============|===========|=============|==============|============-- -- 37-72 | "36Kb" | 512 | 9-bit | 8-bit -- -- 19-36 | "36Kb" | 1024 | 10-bit | 4-bit -- -- 19-36 | "18Kb" | 512 | 9-bit | 4-bit -- -- 10-18 | "36Kb" | 2048 | 11-bit | 2-bit -- -- 10-18 | "18Kb" | 1024 | 10-bit | 2-bit -- -- 5-9 | "36Kb" | 4096 | 12-bit | 1-bit -- -- 5-9 | "18Kb" | 2048 | 11-bit | 1-bit -- -- 3-4 | "36Kb" | 8192 | 13-bit | 1-bit -- -- 3-4 | "18Kb" | 4096 | 12-bit | 1-bit -- -- 2 | "36Kb" | 16384 | 14-bit | 1-bit -- -- 2 | "18Kb" | 8192 | 13-bit | 1-bit -- -- 1 | "36Kb" | 32768 | 15-bit | 1-bit -- -- 1 | "18Kb" | 16384 | 14-bit | 1-bit -- ----------------------------------------------------------------------- BRAM_SDP_MACRO_inst : BRAM_SDP_MACRO generic map ( BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb" DEVICE => "VIRTEX6", -- Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6" WRITE_WIDTH => 0, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb") READ_WIDTH => 0, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb") DO_REG => 0, -- Optional output register (0 or 1) INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY", -- "GENERATE_X_ONLY" or "NONE" SRVAL => X"000000000000000000", -- Set/Reset value for port output INIT => X"000000000000000000", -- Initial values on output port -- The following INIT_xx declarations specify the initial contents of the RAM INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", -- The next set of INIT_xx are valid when configured as 36Kb INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", -- The next set of INITP_xx are for the parity bits INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", -- The next set of INIT_xx are valid when configured as 36Kb INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000") port map ( DO => DO, -- Output read data port, width defined by READ_WIDTH parameter DI => DI, -- Input write data port, width defined by WRITE_WIDTH parameter RDADDR => RDADDR, -- Input read address, width defined by read port depth RDCLK => RDCLK, -- 1-bit input read clock RDEN => RDEN, -- 1-bit input read port enable REGCE => REGCE, -- 1-bit input read output register enable RST => RST, -- 1-bit input reset WE => WE, -- Input write enable, width defined by write port depth WRADDR => WRADDR, -- Input write address, width defined by write port depth WRCLK => WRCLK, -- 1-bit input write clock WREN => WREN -- 1-bit input write port enable ); -- End of BRAM_SDP_MACRO_inst instantiation Help on this would be much helpful! |
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