输出启用怎么设置

你好，
我相信这是你正在寻找的：在PATA中，你需要一些引脚作为O/P和一些其他引脚作为I/P引脚。
假设，如果你想要端口A.0作为O/P，其余的引脚作为输入，那么你可以指定：
OEA＝0x01；//仅PORTA。0作为O/P启用。
同样，如果你想要，比如说POTA。0, 3, 5作为O/P引脚，那么
OEA＝0x29；//PORTA.0，3，5作为O/P引脚启用
OEA是端口的O/P使能寄存器。即，通过在OEA中设置适当的位，端口的适当位可以被配置为O/P。
然而，IOA反映了门户的状态。如果您想将任何特定的值赋给POTA的O/P PIN，则将特定值分配给IOA的APPRORITY位。类似地，为了读取PATA的输入引脚的值，可以从IOA的适当位读取它。
说，如果你想做
-PoTa. 0作为O/P引脚并使其高
-波尔塔。1作为I/P PIN并读取其状态。
然后
OEA＝0x01；//PORTA。0作为O/P引脚启用。
IOA＝0x01；//设置PATA。0为高。
Va＆Gt；＝IOA＆AM0x02；/读状态PATA。1。
我相信这就是你要找的东西。
当做，
加亚特里



     以下为原文
   Hi,
     
    I believe this is what you are looking for: in portA , you want some of the pins to act as O/P and some other pins as I/P pins.
    SAy, if you want port A.0 to act as O/P and rest of the pins as input, then you can assign:
    OEA = 0x01; // only portA.0 is enabled as O/P
    Similarly, if you want, say portA.0, 3, 5 as O/P pins, then
    OEA = 0x29;  //portA.0,3,5 enabled as O/P pins
     
    OEA is the O/P enable register for portA. i.e. by setting the appropriate bit in OEA, the appropriate bit of portA can be configured as O/P.
    Whereas, IOA reflects the portA status. If you want to assign any particular value to O/P pin of portA, then assign the particular value to the approriate bit of IOA. Similarly, to read the value at the input pin of portA, you can read it from the appropriate bit of IOA.
    Say, if you want to make
     - portA.0 as O/P pin and make it high
     - PortA.1 as I/P pin and read its status
    then
     OEA = 0x01; //portA.0 is enabled as O/P pin
     IOA |= 0x01; // set portA.0 as high
      = IOA & 0x02; //read status of portA.1
    I believe this is what you are looking for.
     
    Regards,
    Gayathri

你好，
IOA是一个寄存器。写入IOA的值出现在被配置为输出的引脚上；从IOA读取的值指示8个引脚的状态，而不管输入/输出配置。参见TRM第183页的IOX寄存器。
OE X寄存器（其中X是A、B、C、D或E），它设置8个引脚中的每一个的输入/输出方向（0＝输入，1＝OUT PUT）。因此，您可以根据您的需求设置引脚。
当做
普拉吉斯



     以下为原文
  Hi,
    An IOA is a register. Values written to IOA appear on the pins which are configured as outputs; values read from IOA indicate the states of the 8 pins, regardless of input/output configuration. See IOx register on page  183 of TRM .
    An OE x register (where x is A, B, C, D, or E), which sets the input/output direction of each of the 8 pins (0 = input, 1 = out-put). So, you can set the pins based on your requirements.
    Regards
    Prajith

您好!
实际上，如果我想在FX2LP 128AXC中输入输入方向IFCK引脚和SLWR，那么我要做什么设置呢？



     以下为原文
   Hi 
    For acutually, If i want make input direction IFCLK pin and SLWR in  FX2LP 128AXC, then what am i do for setting?

您好!
实际上，如果我想在FX2LP 128AXC中输入输入方向IFCK引脚和SLWR，那么我要做什么设置呢？
我认为SLWR和IFCK没有被指定为端口PIN。同样，许多引脚也没有分配。
除了PA、PB等端口插针之外。
所以，我怎么做，如IFCK SLWR，FLAGA…等插脚？



     以下为原文
   [size=10.909090995788574px] Hi 
    [size=10.909090995788574px]For acutually, If i want make input direction IFCLK pin and SLWR in  FX2LP 128AXC, then what am i do for setting?
    [size=10.909090995788574px] 
    [size=10.909090995788574px]i think SLWR and IFCLK is not assigned as Port Pin. Also So many pins are also not assigned.
    [size=10.909090995788574px] 
    [size=10.909090995788574px]except for PA#,PB#,etc...Port Pins.
    [size=10.909090995788574px] 
    [size=10.909090995788574px]So, how i do such as IFCLK SLWR, FLAGA ... etc pins?

你好，
SLWR是FX2LP的输入信号，SLWR引脚应该由Mistin断言，以便将数据写入FIFO。在同步模式（IFCONFIG。3＝0）中，FSD-BISIS的数据写入IFFO（FIFO指针递增）在IFLK的每个上升沿上，而SLWR被断言。非异步模式（IFCONFIG 3＝1），FD总线的数据写入到FIFO（和FIFO指针递增）上，每个SLWR断言为断言的过渡。默认情况下，SLWR为低电平；其极性可以通过FIFOP极性寄存器改变。
IFCLK既可以用作外部时钟源，也可以用于外部设备提供时钟。IfCONFIG.7在内部和外部源之间选择：0＝外部，1＝内部。如果选择外部IFCK，它必须在5 MHz的最小频率下自由运行。此外，为了为内部端点FIFO逻辑提供同步，必须在固件集IFCONFIG 7＝0之前存在外部IFCK源。
标志引脚是输出引脚，提供了EZ-USB的FIFOS的状态。
当做
普拉吉斯



     以下为原文
   Hi,
    SLWR is an input signal to FX2LP,SLWR pin should be asserted by the master in order to write data to the FIFO. In synchronous mode (IFCONFIG.3 = 0), data on the FD bus is written to the FIFO (and the FIFO pointer is incremented) on each rising edge of IFCLK while SLWR is asserted. In asynchronous mode (IFCONFIG.3 = 1), data on the FD bus is written to the FIFO (and the FIFO pointer is incremented) on each asserted-to-deasserted transition of SLWR. By default, SLWR is active-low; its polarity can be changed via the FIFOPINPOLAR register.
     
    IFCLK can be used either as external clock source or for providing clock to external device. IFCONFIG.7 selects between internal and external sources: 0 = external, 1 = internal. If an external IFCLK is chosen, it must be free running at a minimum frequency of 5 MHz. In addition, in order to provide synchronization for the internal endpoint FIFO logic, the external IFCLK source must be present before the firmware sets IFCONFIG.7 = 0.
    FLAG pins are out put pins which provides the status of  the EZ-USB’s FIFOs.
    Regards
    Prajith

好的，我明白了。
谢谢。



     以下为原文
  Ok i see.
    Thanks a lot. 

不客气



     以下为原文
   You are welcome