在寄存器中不能调整SYSCL

你如何确定PLL的设置没有区别？如何设置PLL？



      以下为原文

    How are you determining that setting the pll makes no difference?
How are you setting the PLL ?

37 DMIPS是微MIPS核心与频率相乘的标准基准结果。这主要是一个没有实际意义的营销数字。使用3xPLL（8x 3）内置振荡器可以获得的最大频率是24MHz。使用OSCTUN可以稍微增加频率，但是没有太大区别。如果PLL不工作，则设置不正确。



      以下为原文

   


37 DMIPS is a standard benchmark result for the MicroMIPS core multiplied by the frequency. This is mostly a marketing number which doesn't have any real life meaning.
 
The maximum frequency you can get with internal oscillator is 24 MHz using 3xPLL (8 x 3). You may increase the frequency slightly with OSCTUN, but it won't make much difference.
 
If PLL is not working, you're not setting it up correctly.
 

生成的mcc.c文件集SPLLCON=0x10080；//PLLODIV 1:1；PLLMULT 3x；PLLICLK FRC；当我在ICD3中读回它时，它读取相同的值CLKSTAT=0x0；同样在OSCILLATOR_Initialize中设置，当我在ICD3中读回这个值时，我得到0，我希望SPLLRDY、SPDIVRDY、FRCRDY为1；mcc.c：void OSCILLATOR_Initialize(void){SYSTEM_RegUnlock();//CF无时钟故障；FRCDIV FRC/1；SLPEN设备在发出等待指令时将进入空闲模式；NOSC FRCDIV；SOSC禁用；CLKLOCK时钟和PLL选择没有被锁定并且可以修改；OSWEN Complete；OSCCON=0x0；//调谐中心频率；OSCTUN=0x0；//PLLODIV 1:1；PLLMULT 3x；PLLICLK FRC；SPLLCON=0x10080；//SWRST禁用；RSWRST=0x0；//WDTO禁用；GNMI禁用；CF禁用；WDTS禁用；NMNT 0；LVD禁用；SWNMI禁用；RNMICON=0x0；//SBOREN禁用；VREGS禁用；RETEN禁用；PWRCON=0x0；SYSTEM_RegLock()；//WDTO禁用；EXTR禁用；POR禁用；睡眠禁用；BOR禁用；PORIO禁用；IDLE禁用；PORCORE禁用；BCFGERR禁用；CMR禁用；BCFGFAIL禁用；SWR禁用；RCON=0x0；//ON禁用；DIVSWEN禁用；RSLP禁用ROSEL SYSCLK；OE禁用；SIDL禁用；RODIV 0；REFO1CON=0x0；//ROTRIM 0；REFO1TRIM=0x0；//SPDIVRDY禁用；CLKSTAT=0x0；}



      以下为原文

   

The generated  mcc.c file sets
    SPLLCON = 0x10080;      // PLLODIV 1:1; PLLMULT 3x; PLLICLK FRC;
When I read it back in ICD3 it reads this same value


CLKSTAT = 0x0; also get set in OSCILLATOR_Initialize,  When I read this back in ICD3 I get 0, I would expect
SPLLRDY,SPDIVRDY,FRCRDY to be 1;



mcc.c:
void OSCILLATOR_Initialize(void)
{
    SYSTEM_RegUnlock();
    // CF No Clock Failure; FRCDIV FRC/1; SLPEN Device will enter Idle mode when a WAIT instruction is issued; NOSC FRCDIV; SOSCEN disabled; CLKLOCK Clock and PLL selections are not locked and may be modified; OSWEN Complete;
    OSCCON = 0x0;
    // TUN Center frequency;
    OSCTUN = 0x0;
     // PLLODIV 1:1; PLLMULT 3x; PLLICLK FRC;
    SPLLCON = 0x10080;
    // SWRST disabled;
    RSWRST = 0x0;
    // WDTO disabled; GNMI disabled; CF disabled; WDTS disabled; NMICNT 0; LVD disabled; SWNMI disabled;
    RNMICON = 0x0;
    // SBOREN disabled; VREGS disabled; RETEN disabled;
    PWRCON = 0x0;
    SYSTEM_RegLock();
    // WDTO disabled; EXTR disabled; POR disabled; SLEEP disabled; BOR disabled; PORIO disabled; IDLE disabled; PORCORE disabled; BCFGERR disabled; CMR disabled; BCFGFAIL disabled; SWR disabled;
    RCON = 0x0;
    // ON disabled; DIVSWEN disabled; RSLP disabled; ROSEL SYSCLK; OE disabled; SIDL disabled; RODIV 0;
    REFO1CON = 0x0;
    // ROTRIM 0;
    REFO1TRIM = 0x0;
    // SPDIVRDY disabled;
    CLKSTAT = 0x0;
}
 

好的，我发现表59-2inhttp://ww1.micro..com/...eviceDoc/60001329b.pdf非常有用，正确设置配置位使得PLL.pragma config FNOSC=1pragma config POSCMOD=2HOWEVER，MCC没有意识到这一点，因此在MCC配置中，我必须补偿波特率，并且进行交互。铂速率。所以我确信这不是在MCC做这件事的正确方法。还是MCC仍然是WIP？



      以下为原文

     
OK,
I found Table 59-2 in
http://ww1.microchip.com/...eviceDoc/60001329b.pdf
very useful, setting the config bits correctly enables the PLL.
 
#pragma config FNOSC = 1 
#pragma config POSCMOD = 2 
 
HOWEVER, MCC does not apear to be aware of this, so in MCC config I have to compensate the baud rate, and interrupt rate.  So I am sure this is not the right way to do this in MCC. Or is MCC still WIP?