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大家好,
我在我的董事会上看到一个非常有趣的问题。 我的设计使用XC3S200-4VQG100C。 需要在FPGA上工作的代码已经过测试,并且在评估板上正常运行。 我有一个专用电路板,其上安装了这个FPGA和其他模拟和数字组件。 该板具有电源,模拟和数字接地。 电源和模拟/数字地之间有5欧姆电阻。 模拟和数字接地短路。 以下是问题: - 当我将正常代码烧入FPGA时,我可以看到我的数字和模拟地被拉高0.45V。 这是因为这两个地面之间存在电流。 这种下降使得ADC无法正常工作,因为参考输出从3V变为2.54V; - 我将5欧姆值减小到1欧姆,ADC开始工作,但FPGA停止配置。 我检查了VCCO,VCC_AUX,VCCINT,一切都很好。 但FPGA没有配置; - 我写了一个简单的代码来生成方波脉冲并测试电路板,我可以看到FGPA配置为2.5欧姆电阻(电源和模拟/数字地之间)但不是0欧姆或1欧姆; - 如果我对PROM进行编程,它会被编程而没有任何问题; - 我仍然不确定FPGA未配置的原因是什么。 请帮忙! Swarup 以上来自于谷歌翻译 以下为原文 Hi all, I am seeing a very interesting issue on my board. I have a design using XC3S200-4VQG100C. The code that needs to work on the FPGA has been tested and is functional on the evaluation board. I have a proprietary board on which this FPGA has been mounted with other Analog and Digital components. The board has Power, Analog and Digital ground. The power and analog/digital ground have 5 ohm resistor between them. The analog and digital grounds are shorted. Below is the issue: - When I have my normal code burnt into the FPGA, I can see my Digital and Analog Ground being pulled up by 0.45V. This is because there is current flow between these 2 grounds. This drop makes the ADC non-functional as the output of the reference changes from 3V to 2.54V; - I reduced the 5 ohm value to 1 ohms and the ADC started working but the FPGA stopped configuring. I checked VCCO, VCC_AUX, VCCINT and all were perfectly fine. But the FPGA did not configure; - I wrote a simple code to generate a square pulse and tested the board, I could see the FGPA getting configured for 2.5 ohm resistor (between Power and Analog/Digital ground) but not for 0 ohm or 1 ohm; - If I program the PROM it gets programmed without any issues; - I am still not sure what could be the reason for FPGA not getting configured. Please Help! Swarup |
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3个回答
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您的电源连接中是否可能混有2.5V配置电压?
如果连接了2.5V配置轨和3V模拟电压轨,我希望看到这种精确的行为。 以上来自于谷歌翻译 以下为原文 Is it possible you have your 2.5V configuration voltage mixed up in your power connections? If the 2.5V configuration rail and the 3V analog voltage rail were connected, I'd expect to see this precise behavior. |
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嘿约翰,
我想你指的是2.5V和3V电压轨混合起来。 我已经检查了电路板和两个监管机构的轨道并没有混淆。 如果我用0欧姆替换5欧姆电阻器,则所有4个稳压器都显示出完美的轨电压。 它的电阻下降导致GND轨道被拉高。 这个问题可能是由于任何故障无源器件(去耦和旁路电容器或电阻器)造成的吗? 以上来自于谷歌翻译 以下为原文 Hey John, I think what you are pointing is 2.5V and 3V rails getting mixed up. I have checked that on the board and the rail for both regulators are not mixed up. If I replace 5 ohm resistor with 0 ohms all the 4 regulators show perfect rail voltages. Its the drop across the resistor that causes GND rail to be pulled up. Can this issue be due to any malfunctioning passives (decoupling and bypass caps or resistors)? |
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FPGA中的某些东西在5欧姆和0欧姆设置之间是不同的。
它是什么? 我从电压开始 - 你说它们都很好 - 然后继续发出信号。 你有没有任何驱动FPGA的信号,其振幅应该比银行的VCCIO编程的高得多? ESD保护二极管会启动,提高电压(至少在FPGA内部,但我希望可以在任何地方看到)。 查看电压电平和配置信号(时钟,数据)以及FPGA周围的所有电压。 还要仔细检查配置引脚是否是您期望的正确绑定值。 我真诚地怀疑,在连接模拟和数字接地时,“坏被动”与“好”和“坏”操作之间的区别有什么关系。 以上来自于谷歌翻译 以下为原文 Something in the FPGA is different between the 5 ohm and 0 ohm setting. What is it? I'd start with the voltages - you say they're all fine - then proceed to the signals. Do you have any signals driving the FPGA that should be much higher in amplitude than the bank's VCCIO is programmed for? ESD protection diodes would kick in, raising the voltages (at least internal to the FPGA but I'd expect visible anywhere). Look at the voltage levels and configuration signals (clock, data) as well as all voltages around the FPGA. Also double-check that the configuration pins are the proper tied values you expect. I sincerely doubt that "bad passives" would have anything to do with a difference between "good" and "bad" operation when connecting the analog and digital grounds. |
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