BUFG有关于Max Fan的经验法则或建议吗？

我建议你通读UG472。
在第12页，它说：
“每个7系列单片器件有32个全局时钟线，可以为整个器件中的所有顺序资源提供时钟和控制信号。全局时钟缓冲器......驱动全局时钟线，必须用于访问全局时钟线”
所以，是的，一个BUFG可以用于您的设计，但BUFG将仅仅通过FPGA的设计就会受到高扇出的影响。
如果要使用减少扇出的时钟缓冲器，则需要使用区域时钟缓冲区（BUFR，BUFH，BUFIO等）并跨越它们之间的域。
这样可以减少时钟偏差和更高频率的运行，但是您需要更加注意设计时钟，并且可能会在时钟交叉点消耗更多资源。
-约旦
这个签名故意留空。



以下为原文

I suggest you read through UG472.  On page 12, it says the following:
 
"Each 7 series monolithic device has 32 global clock lines that can clock and provide control signals to all sequential resources in the whole device. Global clock buffers ... drive the global clock lines and must be used to access global clock lines"
 
So, yes, one BUFG can be used for your design, but that BUFG will suffer from high fanout simply by the design of the FPGA.  If you want to use clock buffers with reduced fanout, you need to use regional clock buffers (BUFR, BUFH, BUFIO, etc.) and cross the domains between them.  This will give you reduced skew on your clock and the potential to run at higher frequencies, but you need to be more mindful of your design clocking and you might consume more resources at clock boundary crossings.
 
-Jordan
This signature intentionally left blank.

你好。
要添加到Jordon，
如果您正在尝试满足上述mentioend路径的时序，您可以考虑在place_design之后使用phys_opt_design来满足时序要求。
这种物理综合phys_opt_design命令在设计的负松弛路径上执行时序驱动的优化。
优化涉及复制，重定时，保持修复和放置改进。
复制驱动程序，然后在复制的驱动程序之间分配负载，然后自动放置复制的驱动程序。
此可选命令在placement之后运行.phys_opt_designcommand优化当前放置的网表。
通过deault，此选项未启用。
您可以从“实施”设置中启用它。
您可以参考此答复记录，其中包含与phys_opt_design相关的更多信息。
http://www.xilinx.com/support/answers/53986.htm



以下为原文

Hi.
 
To add on to Jordon,
 
If you are trying to meet the timing of the above mentioend path you can consider using phys_opt_design after place_design to meet the timing.
 
This physical synthesis phys_opt_design command performs timing-driven optimization on the negative-slack paths of a design. Optimizations involve replication, retiming, hold fixing, and placement improvement. 
 
Drivers are replicated, then loads are distributed among the replicated drivers, and then the replicated drivers are automatically placed. This optional command is run after placement.
The phys_opt_design command optimizes the current placed netlist. 
 
By deault this option is not enabled.
You can enable it from Implementation settings.
 

 
You can refer to this Answer record which has more info related to phys_opt_design.
http://www.xilinx.com/support/answers/53986.htm
 
 
 
 
 
 

>我的问题是每个人都在告诉我一个主时钟的BUFG，一个V7中的完整设计是可以的。
BUFG是一个全球时钟网络，具有多个缓冲阶段。
10个负载和720,000个负载之间没有时间差异。
>然而，我在Timing Violation中看到以下内容：
您只发布了报告为未通过约束的时间路径的一部分，因此无法完全了解发生的情况。
您发布的部分表示BUFG正在驱动LUT的输入，这不应该完成。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> My problem is that everyone is telling me that one BUFG for a primary clock, for a full design in a V7 is OK. 
A BUFG is a global clock net and has multiple stages of buffering.  There will be no timing difference between 10 loads and 720,000 loads.
 
> And yet I see the following in Timing Violation:
 
You only posted a portion of the timing path that was reported as failing your constraint so it isn't possible to fully understand what is occuring.  The portion that you did post indicates that the BUFG is driving the input of a LUT and this should not be done.
 
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

哦，所以报告完整： 
位置延迟类型Incr（ns）路径（ns）网表资源 
--------------------------------------------------
----------------- ------------------- 
（时钟设计_P0.F0_lclock__1__5上升沿） 
0.000 0.000 r
AU30 IBUFDS 0.000 0.000 r lclock_1_5_0 / O. 
net（fo = 1，routed）1.814 1.814 lclock_1_5 / I. 
BUFGCTRL_X0Y49 BUFGCTRL（Prop_bufgctrl_I0_O） 
0.113 1.927 r lclock_1_5 / bufgctrl_0 / O. 
净（fo = 719275，路由）2.729 4.656 / sdl_to_out [78] / g 
单反交叉[1-> 3] 
SLICE_X22Y531 LUT4（Prop_lut4_I2_O）0.042 4.698 r / sdl_to_out [78] / lut / O 
净（fo = 1，路由）0.000 4.698 / odout_ebb [78] 
SLICE_X22Y531 FDRE r / rdout0ffout [78] / D.
有一个Lut，因为在翻牌前有一个“门控时钟”（有点）。
这仍然是“不 - 不”吗？
谢谢，
==
卡梅尔



以下为原文

oK, so the full report:
 
  Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design__P0.F0_lclock__1__5 rise edge)
                                                      0.000     0.000 r 
    AU30                 IBUFDS                       0.000     0.000 r  lclock_1_5_0/O
                         net (fo=1, routed)           1.814     1.814    lclock_1_5/I
    BUFGCTRL_X0Y49       BUFGCTRL (Prop_bufgctrl_I0_O)
                                                      0.113     1.927 r  lclock_1_5/bufgctrl_0/O
                         net (fo=719275, routed)      2.729     4.656    /sdl_to_out[78]/g
    SLR Crossing[1->3]
    SLICE_X22Y531        LUT4 (Prop_lut4_I2_O)        0.042     4.698 r  /sdl_to_out[78]/lut/O
                         net (fo=1, routed)           0.000     4.698    /odout_ebb[78]
    SLICE_X22Y531        FDRE                                         r  /rdout0ffout[78]/D
 
There is a Lut becuase there is a "gated clock" (sort of) before the Flop.
 
Is this still a "no-no" ?
 
Thanks,
==
Carmel
 

> oK，所以报告完整：
不，它仍然只是一部分。
您没有包含可能包含时序约束，总路径和失败条件的完整信息。
>有一个Lut，因为在翻牌前有一个“门控时钟”（某种程度）。
>这仍然是“禁忌”吗？
门控时钟不应用于FPGA设计中。
您应该将“门”更改为“时钟启用”
门控时钟示例（Verilog）
电话my_clock
分配my_clock = clock＆amp;
门;
总是@（posedge my_clock）
开始 
my_reg
时钟使能示例（Verilog）
总是@（posedge clock）
开始 
如果（门） 
开始 
my_reg
d
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> oK, so the full report:
No, it was still only a portion.  You did not include the full information that would have include the timing constraint, the total path and the failing condition.
 
> There is a Lut becuase there is a "gated clock" (sort of) before the Flop.
> Is this still a "no-no" ?
 
Gated clocks should not be used in FPGA designs.  You should change the "gate" to a "clock enable"
 
Gated Clock Example (Verilog)
wire my_clockassign my_clock = clock & gate;always @ (posedge my_clock)begin   my_reg <= my_dataend Clock Enable Example (Verilog)
always @ (posedge clock)begin   if (gate)   begin      my_reg <= my_data   endend 
 
d
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

嗨，
感谢propt重播和支持。
我的问题是我的设计是基于Latch（ASIC编码风格 - >调试原型），我发现LDE建模发布了数据和门之间的延迟。
所以我试图改造LDE略有不同（通过级联两个LD）以解决这个问题，结果是第二个LD上的伪“门控时钟”，这是报告的内容。
谢谢，
==
卡梅尔



以下为原文

Hi,
Thanks for the propt replay and support.
My problem is that my design is heavily Latch based (ASIC coding style -> prototyping for debug) and I have found issued with LDE modeling where there is a delay between the Data and the Gate.
So I'm trying to remodel the LDE slightly different (by cascading two LD)  in order to solve this issue and the result is a pseudo "gated clock" on the 2nd LD which is what is reported.
Thanks,
==
Carmel
 
 

完整报告：第二次尝试： 
位置延迟类型Incr（ns）路径（ns）网表资源 
--------------------------------------------------
----------------- ------------------- 
（时钟设计_P0.F0_lclock__1__5上升沿） 
0.000 0.000 r
AU30 IBUFDS 0.000 0.000 r lclock_1_5_0 / O. 
net（fo = 1，routed）1.814 1.814 lclock_1_5 / I. 
BUFGCTRL_X0Y49 BUFGCTRL（Prop_bufgctrl_I0_O） 
0.113 1.927 r lclock_1_5 / bufgctrl_0 / O. 
净（fo = 719275，路由）2.729 4.656 / sdl_to_out [78] / g 
单反交叉[1-> 3] 
SLICE_X22Y531 LUT4（Prop_lut4_I2_O）0.042 4.698 r / sdl_to_out [78] / lut / O 
净（fo = 1，路由）0.000 4.698 / odout_ebb [78] 
SLICE_X22Y531 FDRE r / rdout0ffout [78] / D. 
--------------------------------------------------
----------------- ------------------- 
（时钟设计_P0.F0_lclock__1__5上升沿） 
0.000 0.000 r
AU30 IBUFDS 0.000 0.000 r lclock_1_5_0 / O. 
net（fo = 1，routed）1.904 1.904 lclock_1_5 / I. 
BUFGCTRL_X0Y49 BUFGCTRL（Prop_bufgctrl_I0_O） 
0.120 2.024 r lclock_1_5 / bufgctrl_0 / O. 
net（fo = 719275，routed）2.752 4.776 / zebu_cto_1 
单反交叉[1-> 3] 
SLICE_X22Y531 r / rdout0ffout [78] / C. 
钟悲观0.000 4.776
单反补偿0.705 5.481
时钟不确定度0.035 5.516
SLICE_X22Y531 FDRE（Hold_fdre_C_D）0.255 5.771 / rdout0ffout [78] 
--------------------------------------------------
----------------- 
所需时间-5.771
到达时间4.698
--------------------------------------------------
----------------- 
松弛-1.073



以下为原文

Full report : 2nd try:
 
  Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design__P0.F0_lclock__1__5 rise edge)
                                                      0.000     0.000 r 
    AU30                 IBUFDS                       0.000     0.000 r  lclock_1_5_0/O
                         net (fo=1, routed)           1.814     1.814    lclock_1_5/I
    BUFGCTRL_X0Y49       BUFGCTRL (Prop_bufgctrl_I0_O)
                                                      0.113     1.927 r  lclock_1_5/bufgctrl_0/O
                         net (fo=719275, routed)      2.729     4.656    /sdl_to_out[78]/g
    SLR Crossing[1->3]
    SLICE_X22Y531        LUT4 (Prop_lut4_I2_O)        0.042     4.698 r  /sdl_to_out[78]/lut/O
                         net (fo=1, routed)           0.000     4.698   /odout_ebb[78]
    SLICE_X22Y531        FDRE                                         r /rdout0ffout[78]/D
  -------------------------------------------------------------------    -------------------
 
                         (clock design__P0.F0_lclock__1__5 rise edge)
                                                      0.000     0.000 r 
    AU30                 IBUFDS                       0.000     0.000 r  lclock_1_5_0/O
                         net (fo=1, routed)           1.904     1.904    lclock_1_5/I
    BUFGCTRL_X0Y49       BUFGCTRL (Prop_bufgctrl_I0_O)
                                                      0.120     2.024 r  lclock_1_5/bufgctrl_0/O
                         net (fo=719275, routed)      2.752     4.776   /zebu_cto_1
    SLR Crossing[1->3]
    SLICE_X22Y531                                                     r  /rdout0ffout[78]/C
                         clock pessimism              0.000     4.776   
                         inter-SLR compensation       0.705     5.481   
                         clock uncertainty            0.035     5.516   
    SLICE_X22Y531        FDRE (Hold_fdre_C_D)         0.255     5.771    /rdout0ffout[78]
  -------------------------------------------------------------------
                         required time                         -5.771   
                         arrival time                           4.698   
  -------------------------------------------------------------------
                         slack                                 -1.073   
 

更多信息，但仍然不是整套信息。
此外，请使用代码插入按钮（带有剪贴板的图标和“C”）使报告可读。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

More information, but still not the whole set of information.   Also, please use the code insertion button (the icon with the clipboard and the "C") to make the report readable.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com