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在Spartan 6设计中,我想运行具有3个不同时钟的抽取流。 假设所有时钟都由DCM_SP或PLL_BASE产生。 那么如果有2个时钟,我会使用BUFGMUX。 如果我需要在3个时钟之间选择,可以级联两个BUGMUX吗? 或许更好的解决方案,或“不要那样做”的理由存在,将适应共享。 提前致谢。 以上来自于谷歌翻译 以下为原文 Hello! In Spartan 6 design I'd like to run decimated streams with 3 different clocks. Assume all the clocks are produced by either DCM_SP or PLL_BASE. Then if there were 2 clocks, I would use BUFGMUX. If I need to select between 3 clocks, is that OK to cascade two BUGMUX's? Perhaps better solution, or reason for "don't do that" exists, would appresiate sharing. Thanks in advance. |
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嗨,是的,您可以使用两个BUFGMUX来复用三个时钟。假设clk1,clk2和clk3是PLL的输出。请按照以下步骤复用3个clock-1。
将clk1和clk2驱动到BUFGMUX1。 假设BUFGMUX的输出是clkout1.2。 使用clk3和clkout1驱动BUFGMUX2。 请确保您使用的BUFGMUX彼此相邻以避免放置问题。请参阅http://forums.xilinx.com/t5/Virtex-Family-FPGAs/3-Input-clock-mux-using-Virtex- 5 / td-p / 67767以及。克里希纳 -------------------------------------------------- ---------------------------------------------请将帖子标记为 如果提供的信息能够回答您的问题/解决您的问题,请“接受为解决方案”。给予您认为有用的帖子。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Hi, Yes, you can use two BUFGMUXs to mux three clocks. Assume that clk1,clk2 and clk3 are outputs of your PLL.Please follow the below steps to mux 3 clocks- 1. Drive clk1 and clk2 to BUFGMUX1. Say that the output of BUFGMUX is clkout1. 2. Drive BUFGMUX2 with clk3 and clkout1. Please make sure that the BUFGMUX you use are adjacent to each other to avoid placement issues. Refer to http://forums.xilinx.com/t5/Virtex-Family-FPGAs/3-Input-clock-mux-using-Virtex-5/td-p/67767 as well. Regards, Krishna ----------------------------------------------------------------------------------------------- Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue. Give Kudos to a post which you think is helpful.View solution in original post |
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嗨,是的,您可以使用两个BUFGMUX来复用三个时钟。假设clk1,clk2和clk3是PLL的输出。请按照以下步骤复用3个clock-1。
将clk1和clk2驱动到BUFGMUX1。 假设BUFGMUX的输出是clkout1.2。 使用clk3和clkout1驱动BUFGMUX2。 请确保您使用的BUFGMUX彼此相邻以避免放置问题。请参阅http://forums.xilinx.com/t5/Virtex-Family-FPGAs/3-Input-clock-mux-using-Virtex- 5 / td-p / 67767以及。克里希纳 -------------------------------------------------- ---------------------------------------------请将帖子标记为 如果提供的信息能够回答您的问题/解决您的问题,请“接受为解决方案”。给予您认为有用的帖子。 以上来自于谷歌翻译 以下为原文 Hi, Yes, you can use two BUFGMUXs to mux three clocks. Assume that clk1,clk2 and clk3 are outputs of your PLL.Please follow the below steps to mux 3 clocks- 1. Drive clk1 and clk2 to BUFGMUX1. Say that the output of BUFGMUX is clkout1. 2. Drive BUFGMUX2 with clk3 and clkout1. Please make sure that the BUFGMUX you use are adjacent to each other to avoid placement issues. Refer to http://forums.xilinx.com/t5/Virtex-Family-FPGAs/3-Input-clock-mux-using-Virtex-5/td-p/67767 as well. Regards, Krishna ----------------------------------------------------------------------------------------------- Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue. Give Kudos to a post which you think is helpful. |
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是的,是可以的。
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