正确的范围界限不是恒定的

嗨gszakacs， 
感谢您的回复。我以不同的方式做了同样的事情。我把循环写成了
因为我在0到160循环
..........
.........
结束循环;
而不是把zone_coverage_s放在循环中我把一个常数。我也尝试了你的方法。但是我遇到的问题是系统正在挂起并且显示出一些内存问题。我附在这里的图像。请看看并帮助我。
错误：可移植性：3  - 此Xilinx应用程序已耗尽
内存或遇到内存冲突。
当前内存使用量为2087368 kb。
您可以尝试增加系统的物理或虚拟内存。
如果您使用的是Win32系统，则可以
使用/中的/ 3G开关将应用程序内存从2GB增加到3GB
boot.ini文件。
有关这方面的更多信息，请参阅Xilinx答案
记录＃14932。
有关此问题的技术支持，您可以使用打开WebCase
这个项目得到了
请访问http://www.xilinx.com/support。
感谢你，Mahesh Hegde。



以下为原文

Hi gszakacs,
                           Thank for your reply.I did the same thing in different way.i wrote the loop as
for i in 0 to 160 loop
..........
.........
end loop;
instead of putting zone_coverage_s in loop i put a constant number.I tried your method also.But i got the problem that system is getting hang and some memory problem is showing.Image i attached here.Please see and help me.
 
ERROR:Portability:3 - This Xilinx application has run out ofmemory or has encountered a memory conflict. Current memory usage is 2087368 kb. You can try increasing your system's physical or virtual memory.  If you are using a Win32 system, you canincrease your application memory from 2GB to 3GB using the /3G switch in yourboot.ini file. For more information on this, please refer to Xilinx AnswerRecord #14932. For technical support on this issue, you can open a WebCase withthis project atta
ched at http://www.xilinx.com/support.
 
Thanks You in Advance,
Mahesh Hegde.

如果您的设计真的很大，那么您可以超过Windows可以支持的虚拟内存量。
所以：1。
只运行ISE.2。
按照错误消息的建议尝试/ 3G开关。
切换到64位操作系统。
想一想让您的设计更小的方法。
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

If your design is REALLY HUGE, then you can exceed the amount of Virtual Memory that Windows can support. So:

1. Only run ISE.
2. Try the /3G switch as advised by the error message.
3. Switch to a 64-bit operating system.
4. Think of a way to make your design smaller.

------------------------------------------
"If it don't work in simulation, it won't work on the board."

嗨， 
正如rcinqham建议的那样，我通过评论一些逻辑将设计逻辑简化为更小的单元。即使我收到此错误消息。我运行的唯一一个应用程序是XILINX ISE。
错误：可移植性：3  - 此Xilinx应用程序已耗尽
内存或遇到内存冲突。
当前内存使用量为2087368 kb。
您可以尝试增加系统的物理或虚拟内存。
如果您使用的是Win32系统，则可以
使用/中的/ 3G开关将应用程序内存从2GB增加到3GB
boot.ini文件。
有关这方面的更多信息，请参阅Xilinx答案
记录＃14932。
有关此问题的技术支持，您可以使用打开WebCase
这个项目得到了
请访问http://www.xilinx.com/support。
感谢你，Mahesh Hegde。



以下为原文

Hi, 
               As rcinqham suggested me, I redused the design logic into smaller unit by commenting some logic.Even though i am getting this error message.I run the only one application that is XILINX ISE.

 
ERROR:Portability:3 - This Xilinx application has run out ofmemory or has encountered a memory conflict. Current memory usage is 2087368 kb. You can try increasing your system's physical or virtual memory.  If you are using a Win32 system, you canincrease your application memory from 2GB to 3GB using the /3G switch in yourboot.ini file. For more information on this, please refer to Xilinx AnswerRecord #14932. For technical support on this issue, you can open a WebCase withthis project atta
ched at http://www.xilinx.com/support.
 
Thanks You in Advance,
Mahesh Hegde.

如果这个设计适合XC6VLX45，那么它不应该耗尽内存合成。
我怀疑循环中有一些逻辑导致某种指数扩展。
在模拟设计时，您对内存使用有任何问题吗？
有
你能够合成设计的某些部分吗？
当你注释掉一些时
代码，你试图评论循环？
-  Gabor
-  Gabor



以下为原文

If this design fits into the XC6VLX45, then it shouldn't run out of memory synthesizing.
I suspect that there is some logic in a loop that causes some sort of exponential expansion.
Did you have any problems with memory usage when you simulated the design?  Have
you been able to synthesize some portions of the design?  When you commented out some
code, did you try to comment out loops?
 
-- Gabor
-- Gabor

嗨gszakacs， 
我没有模拟这个代码，因为在模拟这个设计我有模拟器问题。我无法模拟测试台和＆amp;
我的代码在一个模拟器中。所以我没有模拟这个
感谢你，Mahesh Hegde。



以下为原文

Hi gszakacs,
                         I didn't simulated this code because in simulating this design i had simulator problem.I am not able to simulate test bench & my code in a single simulator.so i didn't simulated this

Thanks You in Advance,
Mahesh Hegde.

好的，所以你无法模拟你的代码，也无法合成你的代码。
听起来你的代码需要重写。
我会从你使用循环开始。
循环非常适合软件，但对硬件来说真的很糟糕。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

Ok, so you can't simulate your code  and you can't synthesis your code.  Sounds like your code needs to be rewritten.
 
I would start with your use of loops.  Loops are great for software, but are really bad for hardware.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

嗨， 
我认为我的应用程序需要循环。我将从传感器获得连续的图像数据（每个像素的10位）。我应该将这些数据与用户给定的值进行比较。如果像素值大于用户给定的值，我sholud将其设置为FF
否则像素值应该设置为00它被称为二值化图像数据。传感器有2080（列）x4（行）.i应该将2080列分成区域。然后在每个区域中我应该搜索连续00（如果为00）
发现，我将在矩阵3x3中检查00。如果在矩阵中检测到00，则必须生成一个脉冲。 
除了循环之外还有其他方法吗？请..
感谢你，Mahesh Hegde。



以下为原文

Hi,
      I think loops are required for my application.I will get continuous image data from sensor(10 bit of each pixel).I should compare this data with user given value.If pixel value is greater than user given value i sholud set that to FF else that pixel value should be set to 00 it's called as binarising the image data.Sensor is having 2080(column)x4(rows).i should divide 2080 column into zone.Then in each zone i should search for continuous 00(if 00 found,i will check 00 in a matrix 3x3 ).If 00 detected in matrix i have to generate one pulse.
       Is any other way to except loop?Please..
Thanks You in Advance,
Mahesh Hegde.

>我认为我的应用程序需要循环。
循环是HDL的一个相对较新的补充，从不“必需”。
我在代码中使用的唯一循环是用于实例化多个模块或基元，而从不用于逻辑函数。
>我将从传感器（每个像素的10位）获得连续的图像数据。
一世
应该将这些数据与
>用户给定的值。如果像素值更大 
比用户给定的值我sholud设置为FF否则该像素
>价值
应该设置为00，它被称为二值化图像数据。
这是一个简单的流数据功能。
在I / O处捕获10位并使用时钟进行寄存
如果io_data> given_val则next_data = 0xFF else next_data = 0x00
到目前为止没有循环
>传感器有2080（列）x4（行）.i应将2080列分成
zone.Then在每个区域i
>应该搜索连续00（如果找到00，我
将在矩阵3x3中检查00。如果在矩阵i中检测到00
>必须
产生一个脉冲。
这里你的描述不够准确，我无法确定你要做什么功能，但我确信一些计数器和if / then / case语句将正确实现。
您的设计是否需要在一个时钟周期内同时操作2080 x 4 x 10 = 83,200个寄存器？
如果没有，那么你绝对不需要使用循环。
此外，由于看起来您的目标是只有54,576个寄存器的6SLX45，因此设计不可能适合。
您是否为您的设计创建了一个框图？
您的代码是否与程序框图相匹配？
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> I think loops are required for my application.
 
Loops are a relatively recent addition to HDL and are never "required".  The only loops that I use in my code is for instantiation of multiple modules or primitives and never for logic functions.
 
> I will get continuous image data from sensor(10 bit of each pixel). I should compare this data with
> user given value.If pixel value is greater than user given value i sholud set that to FF else that pixel
> value should be set to 00 it's called as binarising the image data.
 
This is a simple streaming data function.

• Capture 10 bits at the I/O and register with clock
  
• If io_data > given_val then next_data = 0xFF else next_data = 0x00
  

No loops so far
 
> Sensor is having 2080(column)x4(rows).i should divide 2080 column into zone.Then in each zone i
> should search for continuous 00(if 00 found,i will check 00 in a matrix 3x3 ).If 00 detected in matrix i
> have to generate one pulse.
 
Your description here isn't precise enough for me to determine what function you are trying to do, but I'm sure that some counters and if/then/case statements will implement this correctly.
 
Does your design call for 2080 x 4 x 10 = 83,200 registers to be operated on simulaneously in one clock cycle?  If not then your use of loops is definitely not required.  Also, since it appears that you were targeting a 6SLX45 which has only 54,576 registers it would be impossible for the design to fit.
 
Do you create a block diagram for your design?  Does your code match the block diagram?
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com