adc spartan 3an的vhdl代码不起作用

你好，
我想配置我的斯巴达3AN的A / D转换器。
我尝试在1.4 V 1.9 V之间转换值。我在论坛上找到一个vhdl代码（见下文），它允许你初始化ADC。但是当我使用这个代码时，它不起作用（没有信号输出）。
我确定了数据表中的所有信号，但我不明白信号SPI_MISO的用处。
这个信号是我问题的根源？
有人会为我提供解决方案或其他代码vhdl吗？library IEEE;
使用IEEE.STD_LOGIC_1164.ALL;
使用IEEE.STD_LOGIC_ARITH.ALL;
使用IEEE.STD_LOGIC_UNSIGNED.ALL;
----如果实例化，则取消注释以下库声明
----本代码中的任何Xilinx原语。
- 图书馆UNISIM;
- 使用UNISIM.VComponents.all;
实体ADC_AMP是
端口（clk50：在STD_LOGIC;
ce_amp：在STD_LOGIC中;
start_conv：在STD_LOGIC中;
SPI_MISO：在std_logic中;
--adc
CONV：输出STD_LOGIC;
--adc
ADC1：输出std_logic_vector（13 downto 0）：=（其他=>'0'）;
ADC2：输出std_logic_vector（13 downto 0）：=（其他=>'0'）;
获取：在std_logic_vector中（7 downto 0）;
AMP_CS：输出STD_LOGIC;
MOSI：出STD_LOGIC;
- 放大器
SCK：出STD_LOGIC）;
结束ADC_AMP;
架构ADC_AMP的行为是
type state_type是（IDLE，START，START2，HI，HI_DUMMY，LO，LO_DUMMY，FINE，IDLE_AD，START_AD，HI_AD，LO_AD，FINE_AD）;
signal next_state，state：state_type;
信号计数器：整数范围0到35：= 0;
信号样本：std_logic;
开始
处理（start_conv，ce_amp，状态，计数器）
变量bit_count：整数范围0到15;
开始
案件状态是
当IDLE =>时
如果ce_amp ='1'那么
next_state
next_state
next_state
如果counter = 2那么
next_state
bit_count：= bit_count + 1;
next_state
如果counter = 2那么
next_state
如果bit_count = 8那么
next_state
next_state
如果start_conv ='1'那么
next_state
next_state
next_state
如果counter = 34那么
next_state
next_state
next_state
SCK
AMP_CS
MOSI
SCK
计数器
SCK
MOSI
AMP_CS
SCK
SCK
SCK
SCK 2和计数器18和计数器
计数器
SCK



以下为原文

hello,
I want to configure the A / D converter of my spartan 3AN.
I try to convert values between 1.4 V 1.9 V.
I find the forum a vhdl code (see below) which allows you to initialize the ADC.
but when I use thise code, it does not works (no signal output).
I identified all the signals from the data sheet, but I did not understand the usefulness of signal SPI_MISO.
this signal is the source of my problem?
someone would have a solution or an another code vhdl for me?library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ADC_AMP is
Port ( clk50 : in STD_LOGIC;
ce_amp : in STD_LOGIC;
start_conv : in STD_LOGIC;
SPI_MISO : in std_logic; --adc
CONV : out STD_LOGIC; --adc
ADC1 : out std_logic_vector(13 downto 0) := (others => '0');
ADC2 : out std_logic_vector(13 downto 0) := (others => '0');
gain : in std_logic_vector(7 downto 0);
AMP_CS : out STD_LOGIC;
MOSI : out STD_LOGIC; -- amp
SCK : out STD_LOGIC);
end ADC_AMP;
architecture Behavioral of ADC_AMP is

type state_type is (IDLE, START,START2,HI,HI_DUMMY,LO,LO_DUMMY,FINE,IDLE_AD, START_AD,HI_AD,LO_AD,FINE_AD);
signal next_state, state : state_type;
signal counter : integer range 0 to 35 :=0;
signal sample : std_logic;
begin


process(start_conv,ce_amp,state,counter)
variable bit_count : integer range 0 to 15;
begin
case state is
when IDLE =>
if ce_amp ='1' then
next_state <= START;
else
next_state <= IDLE;
end if;

when START =>
next_state <= START2;
bit_count :=0;
when START2 =>
next_state <= HI;
when HI =>
if counter = 2 then
next_state <= HI_DUMMY;
else
next_state <= HI;
end if;
when HI_DUMMY =>
bit_count := bit_count + 1;
next_state <= LO;
when LO =>
if counter = 2 then
next_state <= LO_DUMMY;
else
next_state <= LO;
end if;
when LO_DUMMY =>
if bit_count = 8 then
next_state <= FINE;
else
next_state <= HI;
end if;
when FINE =>
next_state <= IDLE_AD;--inizio a campionare

when IDLE_AD =>
if start_conv ='1' then
next_state <= START_AD;
else
next_state <= IDLE_AD;
end if;
when START_AD =>
next_state <= HI_AD;
when HI_AD =>
next_state <= LO_AD;
when LO_AD =>
if counter = 34 then
next_state <= FINE_AD;
else
next_state <= HI_AD;
end if;
when FINE_AD =>
next_state <= IDLE_AD;
when others =>
next_state <= IDLE_AD;
end case;
end process;
process(clk50)
begin
if clk50'event and clk50 ='1' then
state <= next_state;
end if;
end process;
process (clk50)
variable index1 : integer range 0 to 15;
variable index2 : integer range 0 to 15;
begin
if clk50'event and clk50 ='1' then
case state is
when IDLE =>
SCK <= '0';
AMP_CS <= '1';
MOSI <='0';
counter <=0;
when START =>
AMP_CS <= '0';
index1 := 7; -- 8 bit value
when START2 =>
MOSI <= gain(index1); -- ci passo una sola volta dopodichè la assegno in LO_DUMMY

when HI =>

SCK <= '1';
counter <= counter +1;
when HI_DUMMY =>
counter <=0;
when LO =>
SCK <= '0';
counter <= counter +1;
when LO_DUMMY =>
MOSI <= gain(index1);
index1 := index1-1;
counter <=0;
when FINE =>
AMP_CS <='1';
SCK <= '0';
MOSI <= '0';
when IDLE_AD =>
SCK <= '0';
CONV <= '0';
sample <='0';
when START_AD =>
SCK <= '0';
CONV <= '1';
counter <= 0;
sample <='0';
index1 := 13; -- 14 bit value
index2 := 13; -- 14 bit value
when HI_AD =>
SCK <= '1';
CONV <= '0';
counter <= counter +1;
sample <='0';
when LO_AD =>
SCK <= '0';
CONV <= '0';

if(counter >2 and counter < 17) then
-- rappresentazione in complemento a 2
if index1 = 13 then
ADC1(index1) <= not SPI_MISO;
else
ADC1(index1) <= SPI_MISO;
end if;
index1 := index1 -1;
sample <='1';
elsif(counter > 18 and counter < 33) then
-- rappresentazione in complemento a 2
if index2 = 13 then
ADC2(index2) <= not SPI_MISO;
else
ADC2(index2) <= SPI_MISO;
end if;
index2 := index2 -1;
sample <='1';
else
sample <='0';
end if;
when FINE_AD =>
counter <= 0;
sample <='0';
SCK <= '0';
CONV <= '0';
when others =>
SCK <= '0';
CONV <= '0';
AMP_CS <= '1';
MOSI <='0';
end case;
end if;
end process;


end Behavioral;