如何对28位像素数据进行分区以便通过4个串行通道进行传输

CameraLink规范未指定如何对28位像素数据进行分区以便通过4个串行通道进行传输。
我不是CameraLink向导，但这篇维基百科文章有一个非常清晰的位排序图。
该图显示了在所有4个串行通道上以位为单位传输的R，G，B数据。
如果是CameraLink标准文档，这意味着在不违反标准的情况下，位排序可能因制造商而异。
是否有一个普遍接受的de factor标准，比CL标准委员会愿意更进一步？
这些论坛中有许多常驻CameraLink专家，包括Gabor，eilert和bassman。
如果您尚未这样做，则应在论坛中搜索此主题。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
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以下为原文

The CameraLink spec does not specify how the 28 bit pixel data is partitioned for transmission over the 4 serial channels.
 
I'm not a CameraLink wizard, but this Wikipedia article has a pretty clear diagram of the bit ordering.  The diagram shows R,G,B data transported in bits and pieces on all 4 serial channels.
 
If the CameraLink Standard doc, this implies that the bit ordering may vary from manufacturer to manufacturer without violating the standard.  Is there a de factor standard which is commonly accepted, reaching a bit further than the CL standards committees were willing to go?
 
There are a number of resident CameraLink experts in these forums, including Gabor, eilert, and bassman.  If you haven't done so already, you should search the forums on this topic.
 
-- Bob Elkind
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8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.View solution in original post

CameraLink规范未指定如何对28位像素数据进行分区以便通过4个串行通道进行传输。
我不是CameraLink向导，但这篇维基百科文章有一个非常清晰的位排序图。
该图显示了在所有4个串行通道上以位为单位传输的R，G，B数据。
如果是CameraLink标准文档，这意味着在不违反标准的情况下，位排序可能因制造商而异。
是否有一个普遍接受的de factor标准，比CL标准委员会愿意更进一步？
这些论坛中有许多常驻CameraLink专家，包括Gabor，eilert和bassman。
如果您尚未这样做，则应在论坛中搜索此主题。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
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以下为原文

The CameraLink spec does not specify how the 28 bit pixel data is partitioned for transmission over the 4 serial channels.
 
I'm not a CameraLink wizard, but this Wikipedia article has a pretty clear diagram of the bit ordering.  The diagram shows R,G,B data transported in bits and pieces on all 4 serial channels.
 
If the CameraLink Standard doc, this implies that the bit ordering may vary from manufacturer to manufacturer without violating the standard.  Is there a de factor standard which is commonly accepted, reaching a bit further than the CL standards committees were willing to go?
 
There are a number of resident CameraLink experts in these forums, including Gabor, eilert, and bassman.  If you haven't done so already, you should search the forums on this topic.
 
-- Bob Elkind
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serdes是平行加载的，然后连续移出。
这些位移出的顺序是什么？
它是7下降0，还是0到7？
您没有指定要定位的FPGA系列，并且各个系列的OSERDES块可能会以不同的方式运行。
话虽如此，相关的Spartan-6文档UG381，图3-10清楚地显示了输出位顺序为：1到4（即LSB优先）。
没错，并行加载位的编号是1，而不是0。
但等等，这比那更有趣。
如果每个字发送5-8位，则OSERDES块排列在级联的MASTER-SLAVE对中，因为每个OSERDES块每个处理最多4位并行数据。
首先传输SLAVE数据。
因此序列化7位字的传输顺序，LSB优先如下：
SLAVE D1（第一个传输位）
奴役D2
SLAVE D3
SLAVE D4
MASTER D1
MASTER D2
MASTER D3（最后发送的位）
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

The serdes is parallel loaded and then shifted out serially.  In what order are the bits shifted out? Is it 7 downto 0, or 0 upto 7?
 
You don't specify which FPGA family you are targeting, and there is the possibility that the OSERDES blocks for the various families function differently.  Having said that, the relevant Spartan-6 document, UG381, Figure 3-10 clearly shows the output bit order as:  1 upto 4 (i.e. LSB first).  That's right, the parallel load bits are numbered from 1, not from 0.
 
But wait, it's a bit more interesting than that.  If transmitting 5-8 bits per word, the OSERDES blocks are arranged in a cascaded MASTER-SLAVE pair, because each OSERDES block handles up to 4 bits of parallel data, apiece.  The SLAVE data is transmitted first.  So the transmission order for serialising 7-bit words, LSB first is as follows:
 
 SLAVE D1 (first transmitted bit)

 SLAVE D2
 SLAVE D3
 SLAVE D4
MASTER D1
MASTER D2
MASTER D3 (last transmitted bit)
 
-- Bob Elkind
SIGNATURE:
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Summary:
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2. Search the forums (and search the web) for similar topics.
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感谢您的详细回复！
是的，我正在使用Sparten6。
我将尝试维基百科文章中显示的位顺序并发布我的结果。



以下为原文

Thanks for such a detailed response!   Yes, I am using Sparten6.  I'll try the bit order shown in the Wikipedia article and post my results.

当您认为您的问题已得到解答时，请将此主题标记为“已解决”。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
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以下为原文

When you think your questions have been answered, please mark this thread as 'solved'.
 
-- Bob Elkind
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Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

虽然不是Camera Link规范本身的一部分，但是位传输顺序和通道
在国家DS90CR287数据表中清楚地描述了分配。
比特是
遗憾的是，没有以任何明显的方式命令，然后在它上面你有
相机链接层采用28位并对其进行加扰以形成
“端口”和控制信号。
当你设计一个framegrabber时，它会变得更加毛茸茸
需要支持Base / Medium / Full的所有可能配置
Camera Link基于8,10和12位像素的通道分配。
车道
当您添加更多频道链接时，分配甚至不一致
相机链接。
我不得不从相机和framegrabber处理Camera Link
规范的结尾，当你搜索Camera Link时很有意思
spec本身它会引导您进入我们公司的网站。
在这些论坛的某个地方
是另一个让Camera Link在Virtex 5上工作（作为接收器）的线程。
传输方面更容易。
顺便关注时钟
与数据对有明确关系的对 -  3位周期高
并且4位周期为低电平，其上升沿有一个时钟从字边界关闭
如果我的记忆正确地为我服务
当你结束时，你会知道你已经做到了
使用DS90CR288A在另一端接收信号并获得您的预期。
-  Gabor
-  Gabor



以下为原文

While not part of the Camera Link spec itself, the bit transmission order and channel
allocation are clearly described in the National DS90CR287 data sheet.  The bits are
sadly not ordered in any recognizably obvious way, and then on top of it you have the
Camera Link layer which takes the 28 bits and scrambles them around to form
"ports" and control signals.  It gets even hairier when you design a framegrabber
that needs to support all of the possible configurations of Base/Medium/Full
Camera Link based on the lane assignments for 8, 10, and 12 bit pixels.  The lane
assignments are not even consistent as you add more Channel-Links to the
Camera Link.  I've had to deal with Camera Link from both the camera and framegrabber
end of the spec, and it's interesting that when you search for the Camera Link
spec itself it leads you to our company's website.  Somewhere in these forums
is another thread on getting Camera Link working (as a receiver) on Virtex 5.
The transmit side is much easier.  By the way pay close attention to the clock
pair which has a clearly shown relationship to the data pairs - 3 bit periods high
and 4 bit periods low with its rising edge a couple clocks off from a word boundary
if my memory serves me correctly.  You will know you've done it right when you
receive the signal at the other end with a DS90CR288A and get what you expected.
 
-- Gabor
-- Gabor

虽然不是Camera Link规范本身的一部分，但国家DS90CR287数据表中清楚地描述了位传输顺序和通道分配。
Gabor，你的“清楚描述”的想法与我的不同！
似乎缺少的是R / G / B通道位分配表。
维基百科的文章有一个有用的图表，它显示了具有有意义名称的串行位排序（基本配置）。
Wiki文章包含指向Basler的更具描述性的文档的链接，该文档提供了“相机到国家”位映射表。
我认为您需要这两个图来完成FPGA设计和您推荐的解串器检查器（用于验证）。
与此相比，这些标准使其他标准看起来更干净，更优雅。
玩的开心！
Gabor的问题：您对NatSemi（表面上相似）部件DS90CR288A和DS90CR286A之间有偏好吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
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以下为原文

While not part of the Camera Link spec itself, the bit transmission order and channel allocation are clearly described in the National DS90CR287 data sheet.
 
Gabor, your idea of 'clearly described' differs from mine!  What seems to be missing is the table of R/G/B channel bit assignments.
 
The Wikipedia article has a helpful diagram, which shows the serial bit ordering (base config) with meaningful names.  The Wiki article includes a link to a more descriptive doc from Basler, which provides a 'camera-to-National' bit mapping table.  I think you need both of these diagrams to complete both an FPGA design and the deserialiser-checker (for verification) which you recommend.
 
Standards like these make the others look clean and elegant by comparison.  Have fun!
 
Question for Gabor:  Do you have a preference between NatSemi (ostensibly similar) parts DS90CR288A and DS90CR286A?
 
-- Bob Elkind
SIGNATURE:
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2. Search the forums (and search the web) for similar topics.
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维基百科图的问题在于它只显示了许多模式中的一种
Camera Link支持。
规范本身命名端口A到H然后
有一个附录描述了每种模式的端口位的使用，包括
但不限于24位RGB（基本）模式。
我同意Camera Link的规格并不多 - 就像规格一样。
但它比
在Camera Link之前存在的并行AIA“标准”的混乱。
那里
是国家和相机链接之间奇怪的位旋转的一些历史
位编号。
Pulnix的相机已经投入生产，使用的是21位
Channel-Link芯片组而不是28位版本。
我不记得细节
那个相机，但如果你仔细观察，你可以得到你需要的所有信号
在四个数据对中的三个上有一个三抽头6位摄像头。
最后一对只有
三抽头8位摄像头的高两位以及“备用”。
至于国产芯片，如果仔细观察'85 / '86只能覆盖20-66 MHz但是
具有工业温度范围，而'87 / '88A覆盖20-85 MHz，但仅限
商业温度范围。
如果你再向后走，那就是5V
'83 / '84部分也是如此。
问候，
的Gabor
-  Gabor



以下为原文

The problem with the Wikipedia diagram is that it only shows one of many modes
that Camera Link supports.  The spec itself names the ports A through H and then
has an appendix that describes the use of the port bits for each mode, including
but not limited to 24-bit RGB (Base) mode.
 
I agree that Camera Link is not much of a spec - as spec's go.  But it is better than
the morass of bit-parallel AIA "standards" that existed prior to Camera Link.  There
is some history to the strange rotation of bits between the National and Camera Link
bit numbering.  Pulnix had a camera already in production that used the 21-bit
Channel-Link chipset rather than the 28-bit version.  I don't remember the details
of that camera, but if you look closely you can get all the signals you need for
a three-tap 6-bit camera on three of the four data pairs.  The last pair only has
the upper two bits of a three-tap 8-bit camera along with the "spare."
 
As to the National chips, if you look carefully the '85/'86 only cover 20-66 MHz but
have an industrial temperature range while the '87/'88A cover 20-85 MHz but only
a commercial temperature range.  If you go further back there are the 5V
'83/'84 parts as well.
 
Regards,
Gabor
-- Gabor

我几乎错过了你的Basler参考。
他们使用Camera Link扭曲 - 添加一个
80位“Full Camera Link Plus”规范，完全重新排序所有位。
我们的相机
和framegrabbers也支持这些非标准模式。
它涉及抛弃
DVAL和SPARE信号，仅在第2和第3通道链路上复制LVAL。
- 更有趣＆amp;
游戏...
-  Gabor
-  Gabor



以下为原文

I almost missed your Basler reference.  They use Camera Link with a twist - adding an
80-bit "Full Camera Link Plus" spec that completely reorders all of the bits.  Our cameras
and framegrabbers also support these non-standard modes.  It involves ditching the
DVAL and SPARE signals and only replicating LVAL on the 2nd and 3rd Channel-Links.
 
-- More fun & games...
 
-- Gabor
-- Gabor

我几乎错过了你的Basler参考。
他们使用Camera Link扭曲 - 添加一个80位的“Full Camera Link Plus”规范，完全重新排序所有位。
这可能是有用的信息！
:)
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
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以下为原文

I almost missed your Basler reference.  They use Camera Link with a twist - adding an 80-bit "Full Camera Link Plus" spec that completely reorders all of the bits.
 
That might be useful information!  :)
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

gszakacs写道：
我几乎错过了你的Basler参考。
他们使用Camera Link扭曲 - 添加一个
80位“Full Camera Link Plus”规范，完全重新排序所有位。
我们的相机
和framegrabbers也支持这些非标准模式。
它涉及抛弃
DVAL和SPARE信号，仅在第2和第3通道链路上复制LVAL。
- 更有趣＆amp;
游戏...
-  Gabor
我使用Basler格式进行相机输出，扭曲扭曲：我需要8个10位像素而不是10个8位像素，当然帧抓取器不支持那些特别的聪明，所以一些
在保存图像之前，需要在主机中进行后处理。
（我们将研究Matrox将来处理FPGA的事情，以便基于主机的位重组可以在帧捕获器中完成。）
----------------------------是的，我这样做是为了谋生。



以下为原文

gszakacs wrote:
I almost missed your Basler reference.  They use Camera Link with a twist - adding an
80-bit "Full Camera Link Plus" spec that completely reorders all of the bits.  Our cameras
and framegrabbers also support these non-standard modes.  It involves ditching the
DVAL and SPARE signals and only replicating LVAL on the 2nd and 3rd Channel-Links.
 
-- More fun & games...
 
-- Gabor

I used the Basler format for a camera output, with a twist to the twist: I needed eight 10-bit pixels instead of ten 8-bit pixels, and of course the frame grabbers don't support that particular bit of cleverness, so some post-processing in the host needs to happen before images can be saved. (We will investigate Matrox' processing FPGA for something in the future so the host-based bit-reorg can be done in the frame grabber.)
----------------------------Yes, I do this for a living.

鲍勃，
国家数据表只关注串行器和解串器如何排序28个数据位。
没有任何迹象表明您必须使用Camera Link格式与这些部分。
Camera Link规范（例如）描述了各种Camera Link模式的特定位分配。
从广义上讲，有三种模式：Base，Medium和Full，它们使用1,2和3个四通道串行路径。
然后在这些模式中，你有一些“点击”（这不是Camera Link规范中的一个单词），它告诉你每个像素时钟发送了多少个像素，并且每个点击有一些位数（像素字）
宽度）。
RGB只是基本相机LInk上的三个8位分接头，并列在CL规范中。
'288A和'286A之间的差异只是最大时钟频率。
'288A最高可达85 MHz。
我最近没有看过两者之间的价格差异，但我想如果你有多个设计，有些支持85 MHz时钟，有些支持低于66 MHz的设计，我没有理由不使用'288A。
我的意思是，为什么要存两个部分？
----------------------------是的，我这样做是为了谋生。



以下为原文

Bob,
The National datasheets only concern themselves with how the 28 data bits are ordered by the serializer and deserializer. There's nothing that says you have to use a Camera Link format with those parts.
 
The Camera Link spec (such as it is) describes specific bit assignments for the various Camera Link modes. Broadly speaking, there are three modes: Base, Medium and Full, which use 1, 2 and 3 four-lane serial paths. Then within these modes, you have some number of "taps" (which is not a word that's in the Camera Link spec) which tells you how many pixels are sent per pixel clock, and you have some number of bits per tap (pixel word width). RGB is simply three 8-bit taps over Base Camera LInk, and is listed in the CL spec.
 
The difference between the '288A and the '286A is simply the maximum clock frequency. '288A does up to the max of 85 MHz. I haven't looked at price differences between the two very recently, but I suppose there's no reason to not use the '288A if you have multiple designs, some which support the 85 MHz clocking and others that run less than 66 MHz. I mean, why stock two parts? 
----------------------------Yes, I do this for a living.