可以在clk的姿势边缘更改地址吗？

我知道数据在时钟的上升沿读写操作。
您可以选择反转时钟，以使用正时钟边沿或负时钟边沿。
默认（和习惯）使用是时钟的正边缘。
参见UG331（v1.7第164页）第4章使用Block RAM  - 控制输入。
但是，从时序波形来看，时钟到输出延迟是
与从时钟的下降沿到延迟的延迟大致相同
读/写地址更新。
在您的原始帖子中，您特别提到了Spartan 3e。
这很重要，因为各种Spartan 3x系列之间的BRAM功能存在一些差异（参见UG331表4-3）。
Spartan-3e BRAM没有数据输出寄存器。
对于读取，CLK => Q延迟有一个规范：TBCKO。
见DS312表103。
我没有看到Spartan-3e BRAM的“时钟下降沿”时序规范。
如果您有不同的时序参数，请具体说明可能的时序参数。
我应该更新上的读/写地址 
时钟的下降沿确保地址总线的建立/保持时间？
您应该在与用于BRAM的时钟边沿相同的时钟边沿上生成读/写地址。
这为您提供了最大的时序余量（一个完整的时钟周期），并大大简化了时序分析。
换句话说，您应该将BRAM视为设计中的任何其他时钟逻辑。
例如，如果在两个后沿寄存器之间的数据路径中插入一个负边沿寄存器，则会使时序和路由更加复杂。
除非您有特定且令人信服的理由，否则您应该为整个设计坚持一个时钟和一个时钟边缘。
这将以多种方式大大简化您的设计任务。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
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在原帖中查看解决方案



以下为原文

I know the data read and write operats on the positive edge of clock.

You can optionally invert the clocks, to use either the positive or negative clock edge.  Default (and customary) use is the positive edge of the clock.  See UG331 (v1.7 page 164) Chapter 4 Using Block RAM -- Control Inputs.

However, from the timing waveform, the clock-to-out delay is approximately the same as the delay from negative edge of clock to read/write address update.

In your original post, you specifically refered to Spartan 3e.  This is important because there are some differences in BRAM features between the various Spartan 3x families (see UG331 Table 4-3).  The Spartan-3e BRAM does not have a data output register.  For reads, there is a single specification for CLK => Q delay : TBCKO.  See DS312 Table 103.
 
I do not see a "negative edge of clock" timing specification for Spartan-3e BRAM.  If you have a different timing parameter in mind, please be specific which timing parameter it might be.

Should I update the read/write address on the negative edge of clock to ensure the setup/hold time of address bus?

You should generate your read/write address on the same clock edge as the clock edge used for the BRAM.  This give you the greatest timing margin (a full clock period), and greatly simplifies timing analysis.  In other words, you should treat the BRAM as any other clocked logic in your design.
 
For example, if you insert a neg-edge register in a datapath between two pos-edge registers, you will have made timing and routing much more complicated.  Unless you have a specific and compelling reason, you should stick to a single clock and a single clock edge for your entire design.  This will greatly simplify your design task in a number of ways.
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.View solution in original post

我知道数据在时钟的上升沿读写操作。
您可以选择反转时钟，以使用正时钟边沿或负时钟边沿。
默认（和习惯）使用是时钟的正边缘。
参见UG331（v1.7第164页）第4章使用Block RAM  - 控制输入。
但是，从时序波形来看，时钟到输出延迟是
与从时钟的下降沿到延迟的延迟大致相同
读/写地址更新。
在您的原始帖子中，您特别提到了Spartan 3e。
这很重要，因为各种Spartan 3x系列之间的BRAM功能存在一些差异（参见UG331表4-3）。
Spartan-3e BRAM没有数据输出寄存器。
对于读取，CLK => Q延迟有一个规范：TBCKO。
见DS312表103。
我没有看到Spartan-3e BRAM的“时钟下降沿”时序规范。
如果您有不同的时序参数，请具体说明可能的时序参数。
我应该更新上的读/写地址 
时钟的下降沿确保地址总线的建立/保持时间？
您应该在与用于BRAM的时钟边沿相同的时钟边沿上生成读/写地址。
这为您提供了最大的时序余量（一个完整的时钟周期），并大大简化了时序分析。
换句话说，您应该将BRAM视为设计中的任何其他时钟逻辑。
例如，如果在两个后沿寄存器之间的数据路径中插入一个负边沿寄存器，则会使时序和路由更加复杂。
除非您有特定且令人信服的理由，否则您应该为整个设计坚持一个时钟和一个时钟边缘。
这将以多种方式大大简化您的设计任务。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

I know the data read and write operats on the positive edge of clock.

You can optionally invert the clocks, to use either the positive or negative clock edge.  Default (and customary) use is the positive edge of the clock.  See UG331 (v1.7 page 164) Chapter 4 Using Block RAM -- Control Inputs.

However, from the timing waveform, the clock-to-out delay is approximately the same as the delay from negative edge of clock to read/write address update.

In your original post, you specifically refered to Spartan 3e.  This is important because there are some differences in BRAM features between the various Spartan 3x families (see UG331 Table 4-3).  The Spartan-3e BRAM does not have a data output register.  For reads, there is a single specification for CLK => Q delay : TBCKO.  See DS312 Table 103.
 
I do not see a "negative edge of clock" timing specification for Spartan-3e BRAM.  If you have a different timing parameter in mind, please be specific which timing parameter it might be.

Should I update the read/write address on the negative edge of clock to ensure the setup/hold time of address bus?

You should generate your read/write address on the same clock edge as the clock edge used for the BRAM.  This give you the greatest timing margin (a full clock period), and greatly simplifies timing analysis.  In other words, you should treat the BRAM as any other clocked logic in your design.
 
For example, if you insert a neg-edge register in a datapath between two pos-edge registers, you will have made timing and routing much more complicated.  Unless you have a specific and compelling reason, you should stick to a single clock and a single clock edge for your entire design.  This will greatly simplify your design task in a number of ways.
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

>但是，从时序波形来看，时钟到输出延迟是
与...大致相同
>从时钟的下降沿延迟到
读/写地址更新
正如我先前所说，不是这不是真的。
您正在阅读太多的简单波形图。
DIN建立/保持和DOUT clk-to-out始终相对于端口上使用的时钟的正时钟边沿（除非您反转进入端口的时钟然后它相对于负边缘由于
反转）。
当我走出直边并排列数据时，改变到时钟边缘，在我看来它发生在图中所示的下降时钟边缘之前。
但这又是一个图纸，而不是规格，没有提供时间数字。
如果查看数据手册，您将看到BlockRAM数据时钟输出的时序规范。
>我应该在时钟的下降沿更新读/写地址
确保建立/保持时间
>地址总线？
或者FPGA可以为我做这件事
我只是在时钟的正边缘更新地址？
正如我之前所说，用于数据读写的用户逻辑应使用与BlockRAM相同的时钟边沿
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> However, from the timing waveform, the clock-to-out delay is approximately the same as the
> delay from negative edge of clock to read/write address update
 
As I said earlier, no this is not true.  You are reading far too much in to a simple waveform drawing.  The DIN setup/hold and the DOUT clk-to-out are always relative to the postive clock edge of the clock used on the port (unless you invert the clock going into the port and then it is relative to the negative edge due to the inversion).
 
When I get out my straight edge and line up the data out change to the clock edge it appears to me that it happens before the falling clock edge shown on the drawing.  But again this is a drawing and not a specification and no timing numbers are provide.  If you look in the data sheet you will see the timing specification for the BlockRAM data clock-to-out.
 
> Should I update the read/write address on the negative edge of clock to ensure the setup/hold time
> of address bus? Or FPGA can do this for me and I simply update address at the positive edge of clock?
 
As I said earlier, your user logic for data reads and writes should use the same clock edge as the BlockRAM
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

您正在阅读太多的简单波形图。
Ed，似乎没有好的行为（例如，向文档添加大量易于阅读的图表）将不会受到惩罚。
我希望原版海报现在已经设置好了，但是如何简单的波形图（是的，它真的很简单！）可以完全颠倒过来。
好消息是，这种误解仍然很少，仍然引起震惊和怀疑的反应。
让我们希望它保持这种状态。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

You are reading far too much in to a simple waveform drawing.

Ed, it seems that no good deed (e.g. adding lots of easy to read diagrams to the docs) will go un-punished.
 
I hope the original poster has been set straight by now, but it's quite amazing how a simple waveform diagram (and yes, it really IS simple!) can be turned completely upside down.
 
The good news is that this sort of mis-interpretation is yet rare enough to still elicit a response of shock and di***elief.  Let's hope it stays that way.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

你好：
感谢eteam和mcgett的详细解答。
时钟边缘的普遍规则对我有很大的帮助！
最好的Regard.Ninos K.



以下为原文

Hi:
Thanks for eteam and mcgett's detailed answer. And the universal rule of clock edge helps me a lot!
Best Regard.

Ninos K.