怎么知道一个FPGA的良好工作限制的状态数量

状态机中的状态数没有硬性和快速限制。
唯一的限制是您能够保持设计的可管理性，足以进行设计和调试。
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以下为原文

There is no hard and fast limit on the number of states in a state machine.
 
The only limit is your ability to keep the design manageable enough to design and debug.
 
-- Bob Elkind
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README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

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嗨，
谢谢回答:)
你认为我们可以毫无问题地适应2000  -  3000州吗？
（谈论virtex5-6）
沙洛姆



以下为原文

Hi,
Thank for answer :)
 
You think we can fit without any problem 2000 - 3000 states ? ( talking about virtex5-6)
 
Shalom

2000-3000个州需要12-13位编码，这些是现代FPGA的花生，尤其是Virtex-5/6。
即使您为状态选择单热编码，它仍然适合（尽管在这个尺寸下这可能不是很有利）。
看看XST用户指南（[安装目录] / [版本] /ISE_DS/ISE/doc/usenglish/isehelp/xst.pdf），有一章关于FSM编码技术。
阿德里安
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以下为原文

2000-3000 states will need 12-13 bits to encode, which are peanuts for modern FPGAs, especially for the Virtex-5/6. Even if you choose one-hot encoding for the states, it would still fit (although this is probably not very advantageous at this size).
 
Have a look at the XST User Guide ([installation directory]/[version]/ISE_DS/ISE/doc/usenglish/isehelp/xst.pdf), there is a chapter about FSM coding techniques.
 
 
Adrian

Please google your question before asking it.
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谢谢
它很有帮助
沙洛姆



以下为原文

Thank you
Its helpful
 
Shalom

嗨，
虽然FPGA可以解决它，你也可以吗？
我想看看状态图（气泡图）皮毛这样的FSM图纸。
HDL-Source也很长。
对于“简单”的解码器？
顺便问一下，你打算解码什么？
一点点思考：
FSM可以是分层次的，而计数器也是FSM。
因此，当您必须计算需要以某种方式解码的数据流中的字节时，计数器与时钟使能和具有少量控制状态的FSM的组合可以做到这一点。
有一个很好的综合 
Eilert



以下为原文

Hi,
while the FPGA can hande it, can you too?
 
I'd like to see a drawing of the State Diagram (Bubble Chart) fur such a FSM.
Also the HDL-Source will bekome kind of long.
 
For a "simple" decoder? What are you going to decode, by the way?
 
One little hint to think about:
FSMs can be hierarchically, and Counters are also FSMs.
So when you have to count bytes in a datastream that needs to be decoded somehow, a combination of a counter with clock enable and a FSM with a few controlling states can do it.
 
Have a nice synthesis
  Eilert

你好
你对抗柜台和简单的fsm。
但我在一个芯片上谈论了30个不同解码器的50  -  100个状态（当然还有计数器）
Soa Total ~2000州合成
沙洛姆



以下为原文

Hi
 
You right about the counter and simple fsm.
But I m talking about 50 - 100 states(with counters of course) on 30 different decoders on one chip
 
So a Total of ~2000 state to synthesize
 
Shalom

具有3000个状态的FSM与30个FSM非常不同，每个FSM具有100个状态，但是在FPGA上仍然可以很好地实现。
请在询问之前先查询您的问题。如果有人回答您的问题，请在“接受为解决方案”标记该帖子。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的星）。



以下为原文

An FSM with 3000 states is very different from 30 FSMs with 100 states each, which however is still very accomplishable on an FPGA.

Please google your question before asking it.
If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).

嗨，
这是你在那里做的一些奇怪的数学。
您无法总结多个FSM的状态并询问资源需求。
正如之前概述的那样，您只需要12位来编码4096个状态。
与此相比，100个5位FSM只能编码3200个状态，但需要500个位才能存储这些状态。
所以国家的总数是没有意义的。
此外，状态数仅表示用于对这些编码的FF的数量，这取决于编码方案。
但分支和输出所需的逻辑决定了资源的使用和可行的速度。
并且这些可以在零（例如，简单的移位寄存器）和一些非常大量的LUT之间变化。
因此，在您的情况下，最好的方法似乎首先制作单个解码器-FSM。
然后，您可以将所需的资源乘以30，看它是否仍然适合您的FPGA。
（结果也给你一个估计，但是很好。）
创建一个解码器后，您可以将其显示在论坛中，并询问有关如何优化或改进它的提示。
有一个很好的综合 
Eilert



以下为原文

Hi,
that's some strange math you are doing there.
You just can't sum up the states of multiple FSMs and ask for the ressource needs.
As awillen outlined before, you need just 12 bits to encode 4096 states.
Compared to that, 100 5-bit FSMs can only encode 3200 states, but need 500 bits to store these.
 
So the overall number of states is meaningless.
 
Also, the number of states indicates only the number of FFs used to encode these, depending on the coding scheme.
But the logic needed for branches and outputs determine the ressource usage and acheivable speed. And these can vary between zero (e.g. a simple shift register)  and some really big number of LUTs.
 
So, the best approach in your case seems to make a single decoder-FSM first. Then you can multiply the needed ressources by 30 and see if it still fits in your FPGA. (The result also gives you just an estimation, but a good one.)
 
Once you have created one decoder, you can show it to the forum and ask for tips on how to optimize or improve it.
Have a nice synthesis
  Eilert
 
 
 
 

非常感谢你
这很有帮助
沙洛姆



以下为原文

Thank you very much
It was helpful
 
Shalom