xilinx ISE 11.1即使使用了所有输入也会收到错误Xst 647

aaditi写道：
事实上，自从过去2天以来我一直坚持这个问题而且我没有太多的人来引导我。
我真的很感激你的建议n帮助我。
我应该在灵敏度列表中添加什么？
信号'a'？
我每次迭代都会从数组'A1'中分配'a'一个值...它错了吗？
您需要购买和学习一本优秀的VHDL书籍，以了解为什么您的代码无法正常工作。
这非常重要，因为你所做的事情是行不通的。
这绝对是基本的VHDL，你必须理解它。
每次通过循环时，计划将新值分配给信号a。
每个调度的新值（对于循环的每次迭代）都会覆盖先前调度的赋值。
因此，分配给a的是查找表中的值1。
这意味着即使循环迭代48次，也只有一个赋值给a。
但它比你想象的要糟糕。
因为对a使用非阻塞（信号）赋值，所使用的lr_r_ep中的唯一位是位1，由上次触发进程时完成的赋值确定。
（因为它本质上是一个常量赋值，它永远不会改变，所以看起来几乎是正确的。）
所以你的代码有几个问题。
去吧。
----------------------------是的，我这样做是为了谋生。
在原帖中查看解决方案



以下为原文

 

aaditi wrote:
Actually i am stuck at this problem since past 2 days and i didnt have much ppl to guide me around.
 
I am really thankful that u bothered to advice n help me out. What should i add to d sensitivity list? signal 'a'? n i am assigning 'a' one value from the array 'A1' per iteration..hws it gng wrong?

 
You need to buy and study a good VHDL book to see why your code won't work as you hope. This is VERY important, because  what you are doing won't work. This is absolutely basic VHDL and you MUST understand it.
 
Each time through the loop, a new value is scheduled to be assigned to the signal a. Each scheduled new value (for each iteration of the loop) overwrites the previously-scheduled assignment. So what gets assigned to a is the value 1 from the lookup table. This means that even though the loop iterates 48 times, there is only one assignment to a.
 
But it's worse than you think. Because you use a non-blocking (signal) assignment for a, the only bit in lr_r_ep that is used is bit 1, as determined by the assignment to a that was completed the last time the process was triggered. (Since it's essentially a constant assignment, it never changes, so it appears almost correct.)
 
So there are several problems with your code. Get to it.
----------------------------Yes, I do this for a living.View solution in original post

aaditi写道：
我在VHDL代码中遇到问题。
在xylinx ISE 11.1中合成时，会生成以下警告
“警告：Xst：647  - 输入>从不使用。如果该端口属于顶级块或者属于子块，则该端口将被保留并保持未连接状态，并保留该子块的层次结构。”
但是在程序中我通过使用“for loop”使用了所有输入。
您可以查看代码吗？告诉我该怎么做才能克服这个问题。
图书馆IEEE;
使用IEEE.STD_LOGIC_1164.ALL;
使用IEEE.STD_LOGIC_ARITH.ALL;
使用IEEE.STD_LOGIC_UNSIGNED.ALL;
实体ep是
port（lr_r_ep：在std_logic_vector（1到32）; ep_xorp：out std_logic_vector（1到48））;
结束ep;
ep的架构aaditi是
信号a：整数范围0到32;
类型ep_ROM是整数范围1到32的数组（1到48）;
常数A1：ep_ROM：=
（32,1,2,3,4,5，
4,5,6,7,8,9，
8,9,10,11,12,13，
12,13,14,15,16,17，
16,17,18,19,20,21，
20,21,22,23,24,25，
24,25,26,27,28,29，
28,29,30,31,32,1）;
开始
处理（lr_r_ep）
开始
loop1：for 1 in 1 loop 
一个ep_xorp（i）
结束过程;
结束aaditi;
您正在使用非阻塞信号分配（对a的赋值是重要的），您的过程的灵敏度列表是不完整的，因此合成器优化了大部分逻辑。
----------------------------是的，我这样做是为了谋生。



以下为原文

 

aaditi wrote:
 
I am having a problem in a VHDL code. On synthesizing in xylinx ISE 11.1 the following warning is generated "WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved."but in the program i have used all my inputs by using "for loop". Can u please look through the code n tell me what should i do to overcome this prob. library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity ep isport (lr_r_ep : in std_logic_vector (1 to 32); ep_xorp : out std_logic_vector( 1 to 48 ));end ep;architecture aaditi of ep issignal a: integer range 0 to 32;type ep_ROM is array (1 to 48) of integer range 1 to 32;constant A1 : ep_ROM :=(32,     1,    2,     3,     4,    5,  4,     5,    6,     7,     8,    9,  8,     9,   10,    11,    12,   13, 12,    13,   14,    15,    16,   17, 16,    17,   18,    19,    20,   21, 20,    21,   22,    23,    24,   25, 24,    25,   26,    27,    28,   29, 28,    29,   30,    31,    32,    1 );beginprocess(lr_r_ep)beginloop1: for i in 1 to 48 loop             a <= A1(i);             ep_xorp(i) <= lr_r_ep(a);end loop loop1;end process; end aaditi; 
 

You're using non-blocking signal assignments (the assignment to a is what matters), your process's sensitivity list is incomplete, and as a result the synthesizer optimizes away most of the logic.
 
----------------------------Yes, I do this for a living.

事实上，自从过去2天以来我一直坚持这个问题而且我没有太多的人来引导我。
我真的很感激你的建议n帮助我。
我应该在灵敏度列表中添加什么？
信号'a'？
我每次迭代都会从数组'A1'中分配'a'一个值...它错了吗？



以下为原文

Actually i am stuck at this problem since past 2 days and i didnt have much ppl to guide me around.
 
I am really thankful that u bothered to advice n help me out. What should i add to d sensitivity list? signal 'a'? n i am assigning 'a' one value from the array 'A1' per iteration..hws it gng wrong?

aaditi写道：
事实上，自从过去2天以来我一直坚持这个问题而且我没有太多的人来引导我。
我真的很感激你的建议n帮助我。
我应该在灵敏度列表中添加什么？
信号'a'？
我每次迭代都会从数组'A1'中分配'a'一个值...它错了吗？
您需要购买和学习一本优秀的VHDL书籍，以了解为什么您的代码无法正常工作。
这非常重要，因为你所做的事情是行不通的。
这绝对是基本的VHDL，你必须理解它。
每次通过循环时，计划将新值分配给信号a。
每个调度的新值（对于循环的每次迭代）都会覆盖先前调度的赋值。
因此，分配给a的是查找表中的值1。
这意味着即使循环迭代48次，也只有一个赋值给a。
但它比你想象的要糟糕。
因为对a使用非阻塞（信号）赋值，所使用的lr_r_ep中的唯一位是位1，由上次触发进程时完成的赋值确定。
（因为它本质上是一个常量赋值，它永远不会改变，所以看起来几乎是正确的。）
所以你的代码有几个问题。
去吧。
----------------------------是的，我这样做是为了谋生。



以下为原文

 

aaditi wrote:
Actually i am stuck at this problem since past 2 days and i didnt have much ppl to guide me around.
 
I am really thankful that u bothered to advice n help me out. What should i add to d sensitivity list? signal 'a'? n i am assigning 'a' one value from the array 'A1' per iteration..hws it gng wrong?

 
You need to buy and study a good VHDL book to see why your code won't work as you hope. This is VERY important, because  what you are doing won't work. This is absolutely basic VHDL and you MUST understand it.
 
Each time through the loop, a new value is scheduled to be assigned to the signal a. Each scheduled new value (for each iteration of the loop) overwrites the previously-scheduled assignment. So what gets assigned to a is the value 1 from the lookup table. This means that even though the loop iterates 48 times, there is only one assignment to a.
 
But it's worse than you think. Because you use a non-blocking (signal) assignment for a, the only bit in lr_r_ep that is used is bit 1, as determined by the assignment to a that was completed the last time the process was triggered. (Since it's essentially a constant assignment, it never changes, so it appears almost correct.)
 
So there are several problems with your code. Get to it.
----------------------------Yes, I do this for a living.

aaditi写道：
嘿!
非常感谢！
我只是略微修改了我的代码;
从你的建议中得到暗示。
我完全删除了信号'a'，而不是使用：
“ep_xorp
所以问问自己：为什么它现在有效？
并在这里解释。
显示所有工作。
----------------------------是的，我这样做是为了谋生。



以下为原文

 

aaditi wrote:
Hey! Thanks a lot! I just altered my code slightly; taking hint from ur advice.  I removed signal 'a' completely n instead used:
 
" ep_xorp <= lr_r_ep(A1(i)) ; "
 
 n it worked...no warnings...simulation is perfect, etc! thanks a lot again!!  :) :) 

So ask yourself: WHY does it work now?

And explain here. Show all work.

 
----------------------------Yes, I do this for a living.