互斥电路如何降低毛刺概率

在我看来，由于逻辑和路由延迟，这样的电路（具有组合反馈环路）是灾难（或至少是fustration）的一个配方。
如果您可以容忍授权信号的时钟周期延迟，那么使用不同的实现同步生成这些延迟会好得多。
BT



以下为原文

我正在观察路由时序问题。
我做了一个测试电路，正在测试这个故障，它工作正常。
我在原理图中添加了一些IO引脚，这改变了门之间的布线要大得多，现在它有很大的问题。
在这种情况下，任何特定约束是否有用？
我假设有一种方法可以使用锁存器或FF执行此操作，除非以某种优化方式内置到系统中。



以下为原文

I'm observing the routing timing issue.  I made a test circuit that was testing for this glitch and it was working fine.  I added some more IO pins to the schematic, which changed the routing between the gates to be much larger and it has big problems now.
 
Are any particular constraints useful in this type of situation?  I assume there's a way to do this with latches or FFs unless those built-in to the system in some optimized way.

我通过将两条请求线连接到Spartan板上的50mhz和133mhz时钟来测试这个电路。
我通过一个AND门将两个输出连接到一个SR锁存器，看看它是否会出现足够的毛刺以使其跳闸。
它没有。
然后，我将两个从授权引脚中分出的网络分开，一个进入和门，一个进入LED IO引脚，然后开始跳转SR锁存器。
我必须串联3个互斥电路，以便SR锁存器不再跳闸。
当连接到其他引脚时，我得到了相同的结果，似乎连接到IO引脚使得该电路表现得更糟。
我把MAXDELAY约束放在MUTEX电路中的反馈网上，所以现在它们都放在平面图中，我不希望布局再引起这个问题了。
消息由clemahieu于06-06-2009 12:31 AM编辑



以下为原文

I was testing this circuit out by attaching the two request lines to the 50mhz and 133mhz clocks on the Spartan board.  I piped the two outputs through an AND gate and then to an SR latch to see if it would ever glitch enough to trip it.  It didn't.  I then split both of the nets coming out of the grant pins, one going to the and gate and one going to an LED IO pin and then it started to trip the SR latch.  I had to add 3 of the mutex circuits in series in order for the SR latch to not trip again.  I got the same results when connecting to other pins, it seems something about connecting to IO pins makes this circuit behave much worse.
 
I put MAXDELAY constraints on the feedback nets within the MUTEX circuit so now they're all placed close together in the floorplan, I wouldn't expect the layout to be causing this issue anymore.
Message Edited by clemahieu on  06-06-2009 12:31 AM

单独放置解决这个问题可能没有用，因为它也与路由有关（当你连接I / O时会改变）。
通过MAXDELAY控制延迟可能有所帮助，但你真的想要像MAXSKEW这样的东西来限制差异。
即便如此，我怀疑你会再遇到这个电路的问题。
当你试图在FPGA中实现一些异步（带有组合反馈）电路时，这就是野兽的本质 - 这些工具通常是为同步方法设计的。
我会把它重写为一个简单的同步状态机。
BT



以下为原文