上升沿有很多中间状态在x“0000”和x“FFFF”之间

简而言之 - 你无法解决这个问题。
在现实世界中，即在路由后，每个触发器的输出遵循不同的路由路径
到目的地。
您可以想象输出Q1驱动输入D1和Q2驱动D2。
以来
Q1，Q2，D1和D2位于硅的物理上不同的位置，即距离
他们之间是不同的。
因此，如果Q1和Q2同时切换，则D1和D2
由于路由延迟不同，他们的输入会在略有不同的时间发生变化。
在同步设计中，只要路由延迟相对较小即可
时钟周期和建立/保持时间，一切正常。
如果路由延迟也变得太大
设计失败了。
如果您正在解码总线值并使用它来计算更多逻辑，那么您将从根本上得到它
有缺陷的设计 - 你可能会有解码故障。
用于解决此问题的常用技术是使用灰度编码 - 按设计，只使用一种
允许位在每个循环中改变。
这是避免这个问题的绝佳方法
将计数器值从一个时钟域传递到另一个时钟域
希望这可以帮助！
约翰普罗塞纳



以下为原文

Briefly - you can't solve this problem.
 
In the real world, ie, post-route, the output of each flip flop follows a different routing path
to its destinations.  You can imagine that output Q1 drives input D1 and Q2 drives D2. Since
Q1, Q2, D1, and D2 are located in physically different locations on the silicon, the distances
between them are different.  Thus, if both Q1 and Q2 switch at the same time, D1 and D2
will see their inputs change at slightly different times due to the different routing delays.
 
In a synchronous design, as long as the routing delays are relatively small compared to the
clock period and setup/hold times, everything works fine.  If the routing delays become too
long, the design fails.
 
If you are decoding the bus value and using that to clock more logic, you've got a fundamentally
flawed design - you will probably have decode glitches.
 
On common technique used to work around this is to use Gray Coding - by design, only one
bit is allowed to change on each cycle.  This is an excellent way to avoid this problem and to
pass counter values from one clock domain to another.
 
Hope this helps!
 
John Providenza

您所看到的是任何FPGA或ASIC都是正常的。
16位总线上的转换差异只是时钟偏差和净传播延迟（主要是净延迟）。
时序分析将保证所有传播延迟将满足同步系统中下一个寄存器的必要设置和保持时间。
如果要将数据总线从一个时钟域转移到另一个时钟域，那么您需要一个同步器电路，以确保所有数据在进入下一个时钟域之前已先确定。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

What you are seeing is normal for any FPGA or ASIC.  The differences in the transitions across the 16 bit bus is simply do to clock skew and net propogation delays (mostly net delays).
 
Timing analysis will guarantee that all of the propogation delays will meet the necessary set up and hold times to the next register in a synchronous system.
 
If you are transferring the data bus from one clock domain to another then you need a synchronizer circuit to ensure that all of the data has settled first before it is clocked into the next clock domain.
 
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com