Vivado自动插入BUFGCTRL

你好@ rayhaynes
我对你的问题没有任何答案。
但我建议参考以下XAPP585。
我想，解决此问题对您有所帮助。
https://www.xilinx.com/support/documentation/application_notes/xapp585-lvds-source-synch-serdes-clock-multiplication.pdf
最好的祝福，
在原帖中查看解决方案



以下为原文

Hi @rayhaynes
 
I don't have any answer about your question.
But I suggest to refer the following XAPP585.
I guess, it is helpful for you to resolve this issue.
 
https://www.xilinx.com/support/documentation/application_notes/xapp585-lvds-source-synch-serdes-clock-multiplication.pdf
 
Best regards,
View solution in original post

你好@ rayhaynes
我对你的问题没有任何答案。
但我建议参考以下XAPP585。
我想，解决此问题对您有所帮助。
https://www.xilinx.com/support/documentation/application_notes/xapp585-lvds-source-synch-serdes-clock-multiplication.pdf
最好的祝福，



以下为原文

Hi @rayhaynes
 
I don't have any answer about your question.
But I suggest to refer the following XAPP585.
I guess, it is helpful for you to resolve this issue.
 
https://www.xilinx.com/support/documentation/application_notes/xapp585-lvds-source-synch-serdes-clock-multiplication.pdf
 
Best regards,

您试图推断的时钟结构（这些工具似乎允许您在4个银行中的3个中执行）不应该是合法的。
我没有看到任何东西允许时钟“直接”驱动到没有时钟缓冲器的ISERDES。
此外，ISERDES明确指出CLK和CLKDIV必须同相，UG471部分“ISERDES Clocking”专门列出了（仅）两种用于为ISERDES提供时钟的法律机制。
两者中使用BUFIO和BUFR的速度越快，但是，正如您所知，BUFIO的最大时钟频率为710MHz（或速度等级更快的800MHz） - 仍然低于915MHz。
但是你试图获得1830Mbps或915Mbps的比特率（即数据是915MHz SDR还是DDR）。
如果数据是915Mbps，那么你可以在457.5MHz DDR上进行这种计时。
问题是ISERDES在DDR模式下不能做7：1，所以你必须以人工时钟速率进行至少一些操作 - 例如，4：1 DDR。
MMCM可以在DDR模式下为ISERDES生成457MHz时钟，您可以使用4：1反序列化 - 这意味着CLKDIV必须在228.75MHz。
两个时钟都可以驱动到BUFH。
一旦进入228.75MHz域（每个时钟4位），你可以进行结构分组，从4位到7位桶位移（每7个时钟产生4x7位字），并将它们推入FIFO时钟，然后可以
使用130MHz时钟（也由BUFH生成）从FIFO中拉出。
这在结构逻辑方面肯定更复杂 - 你必须手动完成所有的框架，但它使用合法的时钟......
当然，捕获915Mbps接口并非易事。
静态地完成它太快了，因此需要某种动态校准......
Avrum



以下为原文

The clocking structure that you are trying to infer (which the tools appear to let you do in 3 of your 4 banks) should not be legal.
 
There is nothing that I have seen that allows a clock to be driven "directly" to the ISERDES with no clock buffer. Furthermore, the ISERDES specifically states that the CLK and CLKDIV must be in phase, and UG471 section "ISERDES Clocking" specifically lists the (only) two legal mechanism for clocking the ISERDES. The faster of the two uses the BUFIO and BUFR, but, as you realized, the BUFIO maximum clock rate is 710MHz (or 800MHz in faster speed grades) - still too low for your 915MHz.
 
But is the bit rate you are trying to get 1830Mbps or 915Mbps (i.e. is the data 915MHz SDR or DDR). If the data is 915Mbps, then you can do this clocking at 457.5MHz DDR. The problem is that the ISERDES cannot do 7:1 in DDR mode, so you will have to do at least some of the operation at an artificial clock rate - for example, at 4:1 DDR. The MMCM can generate the 457MHz clock for the ISERDES in DDR mode, and you can use 4:1 deserialization - this means that the CLKDIV will have to be at 228.75MHz. Both clocks can be driven to BUFHs.
 
Once in the 228.75MHz domain (at 4 bits per clock) you can do fabric grouping to barrel shift from 4-bits to 7-bits (generating 4x7bit words every 7 clocks), and push them into a clock crossing FIFO, which can then be pulled from the FIFO using a 130MHz clock (also generated by the BUFH).
 
This is definitely more complicated in terms of fabric logic - you will have to do all the framing manually, but it uses legal clocking...
 
Of course, capturing a 915Mbps interface is not trivial. It is way too fast to be done statically, and hence will need some kind of dynamic calibration...
 
Avrum

我想你应该查看你的BUFIO资源。
Vivado可能会为你的一些银行推断一个银行，但由于其他原因可能会耗尽该银行的资源，而是放入一个bufg  - 尽管这绝对不是好事。
您可能有充分的理由将BUFH放在那里，但通常如果您将clk_in直接连接到MMCM，那么您还需要将clk_div_in直接连接到MMCM。
或者，如果我需要一个缓冲区，我会用BUFR驱动clk_div_in，用BUFIO驱动clk_in（vivado可以推断BUFIO，但我更愿意确定，所以我会自己实例化它。）。
至少如果您直接实例化BUFIO并使用LOC约束来锁定资源，如果存在冲突，您应该收到一条错误消息，告诉您它为什么不起作用。
Arik Akerberg，高级FPGA EngineerDesignlinx硬件解决方案公司



以下为原文

I think you should check your BUFIO resources.  It's possible that Vivado is inferring one for some of your banks, but maybe ran out of resources in that bank for other reasons and put in a bufg instead - although that is definitely no good.   
 
You might have good reasons for putting that BUFH in there, but generally if you are connecting clk_in directly to the MMCM then you need to connect clk_div_in directly to the MMCM as well.  
 
Alternately, if I needed a buffer, I would drive clk_div_in with a BUFR and clk_in with a BUFIO (vivado may infer the BUFIO, but I prefer to be sure, so I would instantiate it myself.).  At the very least if you instantiate the BUFIO directly and use a LOC constraint to lock down the resource, if there is a conflict, you should get an error message that tells you why it won't work.  
Arik Akerberg, Senior FPGA Engineer
Designlinx Hardware Solutions, inc

首先，您应该将Vivado设置为不推断时钟缓冲区。
转到“工具” - >“设置”，找到“合成”部分。
将-bufg参数设置为0.默认值为12，这使Vivado可以随时随地插入最多12个时钟缓冲区。
您可能能够使用此时钟路径来使用BUFH元素，但我认为您不可能在没有任何时钟缓冲区的情况下获得直接工作路径。
坦率地说，我没有从这种拓扑结构中获得关键警告。
不要忘记通过接受帖子作为解决方案来尽可能地关闭线程。



以下为原文

As a start, you should set Vivado to not infer clock buffers.   Go to "Tools" -> "Settings", and find the Synthesis section.   set the -bufg parameter to 0.    The default is 12, which lets Vivado randomly insert up to 12 clock buffers wherever it feels needed.    
 
You might be able to get this clock path to work with BUFH elements, but I think it unlikely that you can get a direct path to work without any clock buffer.  I'm frankly surprised you aren't getting CRITICAL WARNING's from this topology.  
Don't forget to close a thread when possible by accepting a post as a solution.

@watari，感谢appnote抬头。
这正是我正在做的事情。
现在我只需要解码他们正在做的诡计以及如何实现它。
我非常担心这不起作用。
@jmcclusk，我将bufgs设置为零，它仍然在该通道中插入一个。
不确定它是什么。
我原本期望一个错误，为什么它需要一个缓冲区而不只是插入一个。
@aakerberg，称我为旧时尚，但我更喜欢实例化所有时钟缓冲器和PLL。
太多的幕后猴子业务否则。
但我认为，自从ISERDES列在933MHz并且PLL输出被列为933MHz它们可以并且由于缓冲器限制必须直接连接在一起。
你的建议是合理的，但不幸的是，没有一种缓冲类型可以直接处理我的915MHz。
@avrumw，我认为你的建议与appnote一致。
我确信我可以使用它，但由于我无法控制内容（即训练序列），因此它会有点棘手。
但由于这是视频，我通过EDID设置时间，希望我可以使用HS，VS和DE进行训练。
我仍然想知道为什么Vivado会让我一直通过Bitgen运行它，并且只有1个严重警告正在执行中，并且由于BUFG插入而导致脉冲宽度错误。
不给我很大的信心。
董事会将在几周后出厂，我想这就是橡胶上路的时候了。
回到编码。
感谢大家的快速反应让我直截了当。
此致，Ray Haynes，Ostendo Technologies，Inc。Carl***ad，CA



以下为原文

@watari, Thanks for the appnote heads up. It's exactly what I'm doing. Now I just need to decode the what trickery they are doing and how to implement it. I was very worried that this was not going to work. 
 
@jmcclusk, I set the bufgs to zero and it still inserted one in that channel. Not sure what it's up to. I would have expected an error about why it needed a buffer and not just insert one.
 
@aakerberg, call me old fashion but I prefer to instantiate all clock buffers and PLLs. Too much behind the scenes monkey business otherwise. But I figured since the ISERDES was listed at 933MHz and the PLL output was listed at 933MHz they could and because of buffer limitations had to be hooked directly together. Your suggestions are sound but unfortunately none of the buffer types will handle my 915MHz directly.
 
@avrumw, I think your suggestion is along the lines of the appnote. I'm sure I can get this to work but since I don't have control of the content (ie training sequence) it's going to be a little tricky. But since this is video and I'm setting the timing via EDID hopefully I can use the HS, VS and DE to train off of.
 
I'm still wondering why Vivado will let me run this all the way through Bitgen and only have 1 critical warning which is in implementation and it's pulse width error because of the BUFG insertion. Doesn't give me a lot of confidence. The board goes out for fab in a couple of weeks, I guess that's when the rubber hits the road. Back to coding. Thanks to everyone for the quick responses setting me straight.
 
Regards, Ray Haynes, Ostendo Technologies, Inc. Carl***ad, CA

@avrumwFYI您可以将PLL / MMCM直接连接到iSERDES。
从UG471第153页
使用网络接口类型的ISERDESE2模块唯一有效的时钟安排是：•由BUFIO驱动的CLK，由BUFR驱动的CLKDIV•由MMCM或PLL驱动的CLK，由相同MMCM或PLL的CLKOUT [0：6]驱动的CLKDIV•CLK驱动
由BUFG，CLKDIV由不同的BUFG驱动
我想我需要做的就是使用PLL的另一个输出来驱动主通道的全局时钟，我本来可以的。
但我继续实施XAPP585，我喜欢它自动校准。
无论如何，谢谢你所有的质量帖子。
我从你的时间关闭帖子中学到了很多东西。
此致，Ray Haynes，Ostendo Technologies，Inc。Carl***ad，CA



以下为原文

 @avrumw FYI you can connect the PLL/MMCM directly to an iSERDES.
 
From UG471 page 153
The only valid clocking arrangements for the ISERDESE2 block using the networking
interface type are:
• CLK driven by BUFIO, CLKDIV driven by BUFR
• CLK driven by MMCM or PLL, CLKDIV driven by CLKOUT[0:6] of same MMCM or PLL
• CLK driven by BUFG, CLKDIV driven by a different BUFG
 
I think all I needed to do is to use another output of the PLL to drive the global clock for the master channel and I would have been ok. But I went ahead in implemented XAPP585 and I like that it auto calibrates. 
 
Anyway thanks for all your quality posts. I have learned a lot from your timing closure posts.
Regards, Ray Haynes, Ostendo Technologies, Inc. Carl***ad, CA