完善资料让更多小伙伴认识你，还能领取20积分哦， 立即完善>
3天内不再提示
电子发烧友论坛|
我有一个中等复杂的设计，花了13个小时来运行实现。
这本身就是令人烦恼的，但令人困惑的是，这一时期的很大一部分似乎来自Vivado，似乎在阶段4.2全球的第1和第2阶段（来自0索引计数）之间闲置。 迭代1完成后，我几乎花了几个小时看着没有输出的日志。 我在晚上离开了它，并且在我第二天到达后报告完成了。 有谁知道全局迭代之间会发生什么，这会导致构建过程长时间旋转？ 它在做什么？ 以上来自于谷歌翻译 以下为原文 I have a moderately complex design that took 13 hours to run implementation. That in and of itself is, bothersome, but the confusing bit is that a big chunk of this time seems to be from Vivado seemingly idling in between interations 1 and 2 (from 0 indexed count) of Phase 4.2 Global. I literally sat through about a couple hours looking at the log with no output after iteration 1 was complete. I left it for the evening and it reported completion after I got in the next day. Does anyone know what's happening in between the Global iterations that would see the build process spin for that long? What is it doing? 
0
|
|
相关推荐
3个回答
|
|
|
|
|
|
2018-10-31 16:47:43
评论
|
|
|
嗨，@ zguo，
还请确认您的设计中没有不合理的时序限制。 -------------------------------------------------- -----------------------不要忘记回答，kudo，并接受为解决方案.------------- -------------------------------------------------- ---------- 以上来自于谷歌翻译 以下为原文 Hi, @zguo, Please also confirm that there is no unreasonable timing constraint in your design. ------------------------------------------------------------------------- Don't forget to reply, kudo, and accept as solution. ------------------------------------------------------------------------- |
|
|
|
|
|
虽然这不是一个小型设计，但我并没有竭尽全力增加额外的时序约束，而Xilinx本身指定的时间限制是PCIe IP内核所必需的。
代码的那部分也没有改变。 此外，它不是一个关于它在全局路由过程中做了什么的问题，而是为什么在两个路由阶段之间似乎存在暂停。 我知道Vivado还在做某事，任务管理器显示CPU和内存使用情况的变化，但就日志而言，很长一段时间它完成了一个路由阶段，甚至没有尝试开始另一个阶段。 以上来自于谷歌翻译 以下为原文 While this is not a small design, I haven't gone out of my way to add additional timing constraints beyond a few that Xilinx itself specifies are necessary for the PCIe IP core. That part of the code was also not changed. Also, it's not so much a question of what it's doing inside of the global routing process, as to why there seems to be a pause in between two of the routing phases. I know Vivado is still doing something, the task manager shows variations in CPU and memory usage, but for a long period of time as far as the log is concerned it's finished one phase of routing and hasn't even attempted to start another phase. |
|
|
|
|
只有小组成员才能发言，加入小组>>
3118 浏览 7 评论
3407 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办？
2874 浏览 9 评论
3966 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区？
3057 浏览 15 评论
请问vc707的电源线是如何连接的，我这边可能出现了缺失元件的情况导致无法供电
1326浏览 1评论
求一块XILINX开发板KC705，VC707，KC105和KCU1500
1168浏览 1评论
/9 
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 （电路图） 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证：合字B2-20210191
工商网监
湘ICP备2023018690号
12122
淘帖
2500
