与两个MMCM共享时钟输入时的严重警告和错误

这可能与您如何生成MMCM有关 - 问题不在于MMCM本身，而在于MMCM前面的IBUFG（实际上只是一个IBUF输入缓冲区）。
最有可能（我猜这里），MMCM没有手工实例化，而是使用时钟向导创建的。
通常，当时钟向导生成时钟核心时，它包括所有缓冲区 
- 输出时钟上的BUFG 
- 关于时钟反馈的BUFG和 
- 驱动输入时钟的IBUFG
当只有一个时钟向导核心由输入时钟驱动时，这很好，但是当你尝试使用两个时，你最终会实例化两个IBUFG（或IBUF）单元。
这是非法的。
FPGA的每个引脚都有一个且只有一个输入缓冲区（IBUF） - 你不能将两个并行放置（这就是上面的消息抱怨）。
因此，您必须修改MMCM的输入。
如果您正在使用时钟向导，则必须从两个时钟核心的输入中移除IBUF，然后在设计的顶层手动实例化IBUF（并将输出馈送到两个时钟核心）。
但是，解决这个问题会产生另一个问题。
用于MMCM的“最佳”输入是与MMCM在同一时钟区域中的四个时钟引脚之一。
但是，在7系列中，每个时钟区域只有一个MMCM。
因此，您无法通过“最佳”输入机制从同一时钟源驱动多个MMCM。
试图这样做会产生另一个严重警告。
这可以通过将另一个MMCM（在不同的时钟区域中）的CLOCK_DEDICATED_ROUTE属性设置为“BACKBONE”来解决，假设它在时钟能力引脚的相邻时钟区域内（即时钟区域上方或下方的时钟区域）
功能引脚和其他MMCM驻留）。
这样做（使用BACKBONE）会增加一些额外的时钟延迟，而这些延迟不会被MMCM补偿 - 这会对使用MMCM在“其他”时钟区域生成的时钟的任何接口的时序产生负面影响（可能
或者对你的设计无关紧要）。
那么，下一个问题是“为什么你需要两个MMCM”？
MMCM可以使用相同的VCO（因此相同的MMCM）生成不同的时钟输出频率和相位。
虽然有些情况下您绝对必须使用两种不同的MMCM，但如果可以的话，通常最好避免这种情况，并将两者结合起来。
那么告诉我们你在做什么需要不同的MMCM，我们可以看看它们是否可能/更好地结合起来。
Avrum



以下为原文

It is probably related to how you generated the MMCMs - the problem is not with the MMCMs themselves, but with the IBUFG (which is really just an IBUF input buffer) that is in front of the MMCM.
 
Most likely (and I am guessing here), the MMCMs were not hand instantiated, but were created using the clocking wizard. Normally, when the clocking wizard generates a clocking core, it includes all buffers
  - the BUFGs on the output clocks
  - the BUFG on the clock feedback and
  - the IBUFG that drives the input clock
 
This is fine when there is only one clock wizard core being driven by an input clock, but when you try and use two, you end up with two IBUFG (or IBUF) cells instantiated. This is illegal. Every pin of the FPGA has one and only one input buffer (IBUF) - you cannot put two in parallel (which is what the message is complaining above).
 
So, you have to modify the inputs to the MMCM. If you are using the clocking wizard, you have to get it to remove the IBUF from the inputs of both clock cores, and then manually instantiate an IBUF at the top level of your design (and feed the output to both clock cores).
 
However, fixing this is going to create another problem. The "best" input to use for an MMCM is one of the four clock capable pins in the same clock region as the MMCM. However, in the 7 series, there is only one MMCM per clock region. Therefore, you cannot drive more than one MMCM from the same clock source via the "best" input mechanism. Trying to do so will generate another critical warning. This can be fixed by setting the CLOCK_DEDICATED_ROUTE property of the other MMCM (in the different clock region) to "BACKBONE" assuming it is in the adjacent clock region to the clock capable pin (i.e. the clock region above or below the one where the clock capable pin and the other MMCM reside).
 
Doing so (using the BACKBONE) adds some additional clock latency that isn't compensated by the MMCM - this will have a negative impact on timing of any interface that uses a clock generated by the MMCM in the "other" clock region (which may or may not matter to your design).
 
So, the next question is "why do you need two MMCMs"? The MMCM can generate different clock output frequencies and phases using the same VCO (hence the same MMCM). While there are cases where you absolutely must use two different MMCMs, it is generally preferable to avoid this situation if you can, and combine the two together. So tell us what you are doing that requires different MMCMs and we can see if it is possible/better to combine them.
 
Avrum

嗨Avrum，
谢谢你的帖子。
我意识到问题是由于单个时钟引脚上的两个IBUF。
我假设综合工具将它们优化为单个IBUF。
由于没有发生这种情况（检查了综合的Verilog网表输出），我手动删除了MMCM内部的IBUF，在MMCM外部实例化了一个IBUF，并将IBUF的输出连接到两个MMCM。
通过此更改，我不会再看到严重警告（并且没有错误）。
有时间失败，我试图看看它们是否可以通过改变设计来解决。
您能告诉我如何检查哪个MMCM放置在时钟引脚的时钟区域中，哪个放置在时钟区域上方/下方？
有没有办法可以让工具将特定的MMCM放在时钟引脚的时钟区域，而另一个MMCM放在上/下的时钟区域？
我需要两个MMCM，因为我需要9个异步时钟 - 每个MMCM最多可以生成7个异步时钟？
我可以通过使用divide_by_2逻辑生成一些时钟来最小化这个数字（9）。
我可以通过放置BUFG并使用create_clock（不是create_generated_clock）约束来在divide_by_2逻辑的输出上定义新时钟吗？
问候，
罗汉



以下为原文

Hi Avrum,
 
Thanks for the post. I realized that the issue is because of the two IBUFs on a single clock pin. I was assuming that the synthesis tool would optimize them to a single IBUF. Since that was not happening (checked the Verilog netlist output of synthesis), I manually removed the IBUFs inside the MMCM, instantiated one IBUF outside the MMCMs and connected the output of the IBUF to the two MMCMs. With this change, I do not see Critical Warnings (and neither the Errors) any more. There are timing failures and I am trying to see if they can be resolved by changing the design.
 
Could you please let me know how to check which MMCM has been placed in the clock pin's clock region and which one is placed in the clock region above/below? Is there a way I can ask the tool to place a specific MMCM in the clock region of the clock pin and the other MMCM in a clock region above/below?
 
I need two MMCMs because I have a requirement of 9 asynchronous clocks - each MMCM can generate a maximum of 7 asynchronous clocks? I can minimize this number (9) by generating some of the clocks using divide_by_2 logic. Will I be able to define a new clock on the output of the divide_by_2 logic by placing a BUFG and using the create_clock (not create_generated_clock) constraint?
 
Regards,
Rohan

您能告诉我如何检查哪个MMCM放置在时钟引脚的时钟区域中，哪个放置在时钟区域上方/下方？
最简单的方法是在Vivado IDE（GUI）中打开设计，并在设备查看器中找到MMCM和时钟引脚。
在器件查看器中，时钟区域（和I / O bank）可清晰识别。
要查找对象，可能最容易从设计的示意图开始，并选择要查找的对象。
在原理图视图中选择对象时，它也会在设备视图中被选中并高亮显示。
有没有办法可以让工具将特定的MMCM放在时钟引脚的时钟区域，而另一个MMCM放在上/下的时钟区域？
引脚的时钟区域只有一个MMCM。
像所有资源一样，FPGA中的站点被命名 -  MMCM位置看起来像MMCME2_ADV_X0Y0
您可以通过设置单元格的LOC属性将单元格放置在站点上。
在您的XDC中，您可以做到
set_property LOC MMCME2_ADV_X0Y0 [get_cells]
我需要两个MMCM，因为我需要9个异步时钟
首先，这是很多时钟......其次，根据定义，来自MMCM的时钟都是彼此同步的。
它们之间的时序关系可能很复杂，但它们是同步的......
我可以通过使用divide_by_2逻辑生成一些时钟来最小化这个数字（9）。
我可以通过放置BUFG并使用create_clock（不是create_generated_clock）约束来在divide_by_2逻辑的输出上定义新时钟吗？
通常不建议使用结构时钟 - 这会在生成的时钟和源时钟之间引入大量偏差。
但是，你说你的时钟是异步的 - 如果你真的不关心时钟之间的关系那么你就可以做到这一点。
生成时钟作为触发器的输出并通过BUFG运行。
生成分频时钟的更好方法是使用BUFGCE或BUFHCE，每隔一个时钟启用“CE”。
这会产生频率为1/2的时钟，输出时钟与输入时钟保持同相。
但是，如果你真的希望时钟是异步的，这并不重要。
当使用BUFGCE / BUFHCE生成时钟时，您需要知道结果时钟的占空比不是50/50  - 除以2，它将是25/75。
最后，无论你做什么（结构分割器或BUFGCE / BUFHCE），我通常会用create_generated_clock限制它 - 这是一个生成的时钟，而不是主时钟。
但是 - 再次 - 如果这些时钟真正异步，这也无所谓......
Avrum



以下为原文

Could you please let me know how to check which MMCM has been placed in the clock pin's clock region and which one is placed in the clock region above/below?
 
The easiest way is to open up the design in the Vivado IDE (the GUI), and locate the MMCMs and the clock pin in the device viewer. In the device viewer, the clock regions (and I/O banks) are clearly identifiable.
 
To find the objects its probably easiest to start with a schematic view of the design, and select the objects you want to locate. When you select an object in the schematic view it is also selected and highighted in the device view.
 
Is there a way I can ask the tool to place a specific MMCM in the clock region of the clock pin and the other MMCM in a clock region above/below?
 
There is only one MMCM in the clock region of the pin. Like all resources, sites within the FPGA are named - the MMCM locations will look something like MMCME2_ADV_X0Y0
 
You can place a cell at a site by setting the LOC property of the cell. In your XDC you can do
 
set_property LOC MMCME2_ADV_X0Y0 [get_cells ]
 
I need two MMCMs because I have a requirement of 9 asynchronous clocks
 
First, that's a lot of clocks... Second, by definition, the clocks coming out of an MMCM are all synchronous with eachother. The timing relationship between them may be complicated, but they are synchronous...
 
I can minimize this number (9) by generating some of the clocks using divide_by_2 logic. Will I be able to define a new clock on the output of the divide_by_2 logic by placing a BUFG and using the create_clock (not create_generated_clock) constraint?
 
It is not generally recommended to use fabric clocks - this introduces lots of skew between the generated clocks and the source clock. However, you say that your clocks are asynchronous - if you really don't care about the relationship between the clocks then you can do this. Generate the clock as the output of a flip-flop and run it through a BUFG.
 
A better way of generating a divided clock is using a BUFGCE or a BUFHCE with the "CE" enabled every other clock. This generates a clock with 1/2 the frequency, and the output clock remains in phase with the input clock. Again, though, if you really want the clocks to be asynchronous this doesn't matter. When the clock is generated with the BUFGCE/BUFHCE you need to be aware that the duty cycle of the resulting clock is not 50/50 - for a divide by 2 it will be 25/75.
 
Finally, regardless of which you do (fabric divider or BUFGCE/BUFHCE) I would normally constrain this with a create_generated_clock - this is a generated clock, not a primary clock. But - again - if these clocks are truly asynchronous, this doesn't matter either...
 
Avrum