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我想澄清在GPIF 2设计师指南,关于“特殊功能”信号OE,我们,DLE,DACK和DRQ的一些含糊不清。
他们的主要文件,在用户指南,第16页,也有讨论在第51页,也在AN8216P13。 1。结合所有这些页面的信息,据我所知,OE和我们做同样的事情。如果这不是真的,那么他们做什么不同呢? 2a。对于信号DLE,UG-P16表示DLE用于将数据锁存到输入级。如果是这样的话,既然它和我们一样,那么这应该是我们和OE之间的区别吧?GPIO 18(W/DLE)执行输入数据捕获和输出驱动器启用/禁用,而GPIOY19仅执行驱动器禁用? 但是,假设UG-P51和AN8216P13是矛盾的,我们知道DLE不是用来捕获输入数据本身,而是为了扩展输入数据保持时间。那是什么?数据捕获,还是扩展输入数据保持时间? 2c,我们和/或DLE与iNi数据动作之间的关系是什么,它似乎能够完全基于其他输入信号捕获输入数据。 三。DRQ和DACK:DOC将DRQ描述为DMA请求(从FX3到外部设备),这似乎很好。但是DOCS将DACK(DMA确认)描述为“用于控制DRQ信号的行为的输入”。这个解释对我来说似乎无关紧要。 DACK的目的当然不是控制DRQ本身。DRQ和DACK肯定一起工作来操作FX3侧状态机,并与外部设备侧的DMA设施交互,以便FX3从外部设备获取数据或发送数据到外部设备。 3A,不清楚DRQ/DACK信号是否直接与FX3内部DMA设备相关,或者是一个单独的机制,可能是为了与外部设备的DMA设施一起工作? 3B。DRQ/DACK如何或不涉及DMANYADE和…水印信号还不清楚。 3C。目前还不清楚DRQ/DACK是否与GPIF状态机分开运行。如果它们需要GPIF状态机,那么这些信号在特定引脚上的意义是什么,因为大概GPIF状态机可以在任何GPIOS上实现这些功能吗? 还有一些其他的含糊不清和差距,但是让我们从这些开始。——Graham 以上来自于百度翻译 以下为原文 I would like to get clarified some ambiguities in the GPIF 2 Designer Guide, regarding "special function" signals OE, WE, DLE, DACK and DRQ. Their primary documentation, is in User Guide, on page 16, and there's also discussion on page 51, and also in AN87216 p13. 1. Combining info on all those pages, so far as I can tell, OE and WE do the same thing. If this is not true, then what do they do different? 2a. For signal DLE, UG-p16 says that DLE is used to latch the data into the input stage. If that's the case, and since it's on the same pin as WE, perhaps that's supposed to be the difference between WE and OE? GPIO 18 (WE/DLE) performs input data capture and output driver enable/disable, while GPIO_19 performs only driver disable? 2b. But that supposition is contradicted by UG-p51 and AN87216 p13 where we learn that DLE is not for capturing the input data per se, but rather just to extend the input data hold time. So which is it? Data capture, or extending input data hold time? 2c. And what is the relationship of WE and/or DLE to the IN_DATA action, which seems able to capture input data based on some other input signals altogether? 3. DRQ and DACK: Docs describe DRQ as DMA Request (from FX3 to external device), which seems fine. But then docs describe DACK (DMA Acknowledge) as "an input that is used to control the behavior of the DRQ signal". This explanation seems nonsensical to me. The purpose of DACK is surely not to control DRQ per se. DRQ and DACK surely work together to operate an FX3-side state machine, and interact with the external-device-side's DMA facility, in order for the FX3 to fetch data from, or send data to, the external device. 3a. It's not clear whether the DRQ/DACK signals relate directly to FX3 internal DMA apparatus, or are a separate mechanism, perhaps intended to work with the DMA facility of the external device? 3b. It's not clear how DRQ/DACK do or don't relate to DMAn_Ready and ...Watermark signals. 3c. It's not clear whether DRQ/DACK operate separately from the GPIF state machine. If they require the GPIF state machine, then what is the significance of these signals being on specific pins, since presumably the GPIF state machine could implement these functions on any GPIOs? There are some other ambiguities and gaps, but let's start with these please. -- Graham |
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3个回答
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OE与读使能一起使用。OE应在读使能信号之前断言两个时钟周期,以便数据总线在FPGA开始读取时准备好数据。
(参见AN6997申请表中的时序图) 以上来自于百度翻译 以下为原文 The OE is used along with the Read enable. OE should be asserted a couple of clock cycles before the read enable signal so that the Data bus is ready with data when the fpga starts reading. (refer timing diagrams in An65974 application note) |
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shinovo 发表于 2018-10-23 19:20 operationred1991_1569406,请指向特定的时序图显示“原厂应该说几个时钟周期在读使能信号”,因为我了解OE的冲突,包括从一个问题。 这一澄清,我想我们谈论的信号叫野莓#,并断言意味着罗。 谢谢。 以上来自于百度翻译 以下为原文 operationred1991_1569406, would you mind pointing to which specific timing diagram shows "OE should be asserted a couple of clock cycles before the read enable signal", because that conflicts with my understanding of OE, including from the AN in question. For this AN, to clarify, I assume we're talking about the signal named SLOE#, and assertion means LO. Thanks. |
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维宏庄小丹 发表于 2018-10-23 19:29 嗨,Graham, 请找出以上问题的答案。 1。OE和我们都提供数据总线上的输出驱动器的直接控制。但是,从UG第51页中可以清楚地看出,我们的断言有助于设置进入路径(在FX3设备中),其中OE是帮助建立出口路径的数据总线方向(FX3之外)的信号。因此,当FX3从主机读取数据时,我们将使用,当FX3将数据写入主设备时,OE将被使用。但是CyPress目前没有一个参考例子,显示了使用OE/WE信号的设计改进。 2A.DLE函数在我们的断言中锁存了几毫秒的数据。因此,我们将用读操作来使用/DLE,但是捕获总是用iNi数据操作来执行。DLE正在增加数据锁存时间,在我们断言的时候,不做数据捕获。这里DLE锁存数据到输入级并不意味着它将捕获数据。 2B. DLE用于延长输入保持时间。 2c. iNoDATA是GPIF操作,可以捕获数据总线上的数据。在UG第51页中讨论的具有示例的状态机显示了如何使用这些信号。W/DLE有助于保持信号以获得有效的采样数据。 三。DRQ和DACK的目的是在这个问题中解释的。文件要传达这两个信号可以一起使用。这些选项是用DRY-DRQ操作提供的。 3A.DACK/DRQ信号旨在与外部设备的DMA设施一起工作。DRRDRQ操作提供了基于DMAYRADE(主动套接字的状态)、GPIF状态机或DACK信号的可能的使用方法。 3b. DMAYRADE选项用于断言DRQ可用。但是不支持基于水印标志的操作。 3D. DRRDRQ断言可以基于DMAYRADE标志或GPIF状态机,这些必须在用户指南中提到的特定PIN。 以上来自于百度翻译 以下为原文 Hi Graham, Please find the answers for the above questions. 1. OE and WE both provides direct control of output drivers on the data bus. But it is clear from UG page 51 that, WE assertion helps in setting up ingress path(in to the FX3 device) where as OE is the signal helps in setting up data bus direction for egress path(out of FX3). So WE is to be used when FX3 reads data from master, where as OE is to be used when FX3 writes data to the master device. But Cypress do not have a reference example currently which shows the improvement in design using OE/WE signals. 2a. DLE function latches the data for few nano-seconds more at the de-assertion of WE. Thus WE/DLE will be used with read operation, but the capture is always performed with the IN_DATA operation. DLE is increasing the data latch time at the time of de-assertion of WE and not doing data capture. Here DLE latches the data to input stage doesn't mean that it will capture the data. 2b. DLE is for extending the input hold time. 2c. IN_DATA is the GPIF operation that can capture the data on data bus. The state machine provided with example discussed in UG page 51 shows how to use the signals. WE/DLE is helping to hold the signal to get valid data on sampling. 3. The purpose of DRQ and DACK is as explained in the question. Documentation wanted to convey that both the signals can be used together. The options are provided with DR_DRQ operations. 3a. DACK/DRQ signals are intended to work with DMA facility of external device. The DR_DRQ operation give possible ways of using this either based on DMA_ready(status of active socket), from GPIF state machine or DACK signals. 3b. The DMA_Ready option to assert DRQ is available. But watermark flag based operations are not supported. 3c. The DR_DRQ assertion can be based on DMA_Ready flag or GPIF state machine, these has to on the specific pin mentioned in the user guide. |
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