是否可以忽略/覆盖所提供IP中的NGC约束

嗨，杰森，
你确定NGC内有限制吗？
用户指南不包含此信息，相反提供了应设置的约束以及在具有核心的UCF中传递的约束。
（所以不在网表内）
＃参考时钟约束
NET“cpri_block_i / gt_and_clocks_i / txoutclk”TNM_NET =“refclkout”;
TIMESPEC“TS_refclk”= PERIOD“refclkout”307.2 MHz;
＃辅助时钟约束
NET“aux_clk”TNM_NET =“aux_clk”;
TIMESPEC“TS_aux_clk”= PERIOD“aux_clk”125.00 MHz;
＃接收时钟
＃这是接收时钟分频器cct的输入
NET“recclk”TNM_NET =“recclk”;
TIMESPEC“TS_recclk”= PERIOD“recclk_int”307.2 MHz;
我见过其他内核提供的NCF约束。
你的目录中有没有这些？
我认为ISE项目目录中的任何NCF文件都会被该工具自动拾取。
对于调试：分析ngdbuild（翻译）BLD报告文件：验证哪些约束文件被拾取和分析，以及这些文件是否与您的设置和您期望的匹配。
否则，是否可以为4.9Gbps重新生成内核？
或者是否可以使用更新版本的核心？
（最新是v8.1）
最好的祝福，
德赖斯
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以下为原文

Hi Jason,
 
are you sure that there are constraints inside the NGC?
The userguide does not contain this information and on the contrary supplies the constraints that should be set and that are delivered in the UCF with the core. (so not inside the netlist)
# Reference clock constraintNET "cpri_block_i/gt_and_clocks_i/txoutclk" TNM_NET = "refclkout";TIMESPEC "TS_refclk" = PERIOD "refclkout" 307.2 MHz;# Auxiliary clock constraintNET “aux_clk” TNM_NET = “aux_clk”;TIMESPEC “TS_aux_clk” = PERIOD “aux_clk” 125.00 MHz;# Receive clock# This is the input to the receive clock divider cctNET “recclk” TNM_NET = “recclk”;TIMESPEC “TS_recclk” = PERIOD “recclk_int” 307.2 MHz; 
I have seen NCF constraints supplied with other cores. Do you have any of those in your directories?
I think any NCF file in your ISE project directory will automatically be picked up by the tool.
 
For debugging: analyze the ngdbuild (translate) BLD report file: verify which constraint files are picked up and analyzed and if these match with your settings and what you expect.
 
Otherwise, is it possible to regenerate the core for 4.9Gbps?
or is it possible to use a newer version of the core? (latest is v8.1)
 
 
Best regards,
Dries
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谢谢Dries，
看看失败的约束我认为我犯了一个错误 - 这看起来像是来自MMCM的推断约束，因此我需要为永远不会达到的情况编辑MMCM分隔符...
那有意义吗？
时序约束：TS_CPRI_CORE_wrapper_cpri_block_i_gt_and_clocks_i_tx_clk_gen_i_clkout0 = PERIOD TIMEGRP“CPRI_CORE_wrapper_cpri_block_i_gt_and_clocks_i_tx_clk_gen_i_clkout0”TS_refclk * 1.25 HIGH 50％;



以下为原文

Thanks Dries,
 
Looking at the constraint that's failing I think I've made an error - This looks like an inferred constraint from an MMCM and therefore I need to edit the MMCM divider for the case that's never reached...
 
does that make sense?
 
Timing constraint: TS_CPRI_CORE_wrapper_cpri_block_i_gt_and_clocks_i_tx_clk_gen_i_clkout0 = PERIOD TIMEGRP "CPRI_CORE_wrapper_cpri_block_i_gt_and_clocks_i_tx_clk_gen_i_clkout0" TS_refclk * 1.25 HIGH 50%;

嗨，杰森，
是的，这更有意义:)
最好的祝福
德赖斯
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以下为原文

Hi Jason,
 
yes, that makes more sense :)
 
 
Best regards
Dries
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简要更新：
驱动用户时钟的MMCM使用动态重新配置，其默认值列在hdl上，工具使用这些来推断最大usrclk速率 - 将默认值编辑为使用最快的配置允许约束降低。
谢谢你的帮助



以下为原文

Brief update:
 
The MMCM driving the user clock uses dynamic reconfiguration, its default values are listed on the hdl and the tool uses these to inferr the max usrclk rate - editing the defaults to the fastest used configuration allows the constraint to come down.
 
Thanks for your help